R

Rambus

Licenses high-speed chip-to-chip connectivity IP

Verification Engineer

Full-TimeDeadline 3/26/27
No salary listed
Senior
Bachelor's, Master's
Aix-en-Provence, France
HybridAt least three days onsite per week; up to two remote days if located in Sofia.
Hardware EngineeringHardware Validation & Testing

About the job

Requirements
  • A Bachelor’s or Master’s degree in Electronics Engineering, Computer Science, or a related discipline.
  • Strong analytical and problem-solving skills.
  • Excellent interpersonal skills.
  • Willingness to travel abroad.
  • Very good English communication skills.
  • At least 6 years of verification experience with Verilog, SystemVerilog, and FPGA prototyping.
  • At least 6 years of experience with complex ASIC/VLSI verification.
  • At least 6 years of experience with Avery or Universal Verification Methodology (UVM).
  • At least 6 years of experience in a multinational company.
Responsibilities
  • Design Verilog register-transfer level (RTL) integrations for different intellectual properties, such as integrating a PCIe IP with a vendor PHY module.
  • Verify IP integration using a dedicated simulation environment.
  • Develop and support test cases for different verification environments.
  • Support worldwide customers with IP integration.
  • Learn the existing verification process and propose improvements.
  • Maintain traceability from customer or product specifications to the architecture and verification results.
  • Track and maintain verification productivity metrics.
  • Report periodically on progress and difficulties.
Desired Qualifications
  • Experience with third-party VIP.
  • Experience creating documentation, using Python, and using shell.

About the company

Rambus designs, develops, and licenses high-speed chip-to-chip connectivity technology. Its IP powers data center servers, AI accelerators, and automotive systems, and is licensed to other semiconductor companies rather than manufactured and sold directly. The products are high-speed interfaces and security features embedded in chips, enabling fast, reliable communication between components. Rambus differentiates itself through a licensing-based model focused on advanced IP for memory, security, and high-speed interfaces across data centers, AI, and automotive markets, rather than relying on a traditional product lineup. The company’s goal is to enable high-performance chip communication at scale by monetizing its intellectual property through licensing and expanding into growing markets like data centers, AI, and automotive.

Company Size

1,001-5,000

Company Stage

IPO

Headquarters

San Jose, California

Founded

1990

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Simplify's Take

What believers are saying

  • Q2 2026 revenue hit $207.4 million, up 20%, with record product revenue.
  • Rambus won a Tier-1 U.S. hyperscaler HBM design win in Q2 2026.
  • Management guides Q3 2026 revenue to $210 million-$216 million, sustaining AI demand.

What critics are saying

  • April 2026 DOJ grand jury subpoena investigates Rambus's alleged DDR5 price-fixing.
  • September 2026 antitrust plaintiffs target Rambus, Montage, and Renesas over RCD pricing.
  • DOJ charges or injunctions cripple Rambus's licensing model and destroy customer trust.

What makes Rambus unique

  • Rambus licenses DDR5, HBM, and security IP inside server memory subsystems.
  • July 27, 2026, Rambus launched DDR5 9600 chipsets and PCIe 7 Switch IP.
  • Its CryptoManager Caliptra root of trust targets data-center and AI SoCs.

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Benefits

  • Health Insurance
  • Dental Insurance
  • Vision Insurance
  • 401(k) Retirement Plan
  • 401(k) Company Match
  • Flexible Work Hours
  • Hybrid Work Options
  • Paid Vacation
  • Gym Membership

Growth & Insights and Company News

Headcount

6 month growth

2%

1 year growth

2%

2 year growth

3%
Yahoo Finance
Oct 16th, 2026
Rambus samples LPDDR6 power chip for AI servers, with analysts eyeing $1.2B revenue by 2029

Rambus has released a power management chip (PMIC) for LPDDR6 SOCAMM2 server memory modules, built for low-power, high-performance AI workloads. The chip is now sampling to lead customers. The product extends Rambus' companion chip line from LPDDR5X SOCAMM2 into the next memory generation. Rambus expects companion chips to reach a mid double-digit share of product revenue by the fourth quarter of 2026. Margins remain a concern. Higher volumes have recently coincided with lower net margin, and tight backend capacity is expected through 2027. An antitrust subpoena adds legal uncertainty. Analysts project revenue of $1.2 billion and earnings of $474.9 million by 2029, up from $239.7 million in earnings today.

Nextronics Times
Oct 14th, 2026
Rambus expands server memory portfolio with LPDDR6 SOCAMM2 power chip.

Rambus expands server memory portfolio with LPDDR6 SOCAMM2 power chip. Rambus (NASDAQ: RMBS) has introduced a power management integrated circuit (PMIC) designed for next-generation LPDDR6 Small Outline Compression Attached Memory Modules (SOCAMM2), targeting the power-efficiency requirements of accelerated artificial intelligence infrastructure. The new chip is being developed in collaboration with customers and ecosystem partners to support future AI servers that require greater memory bandwidth and capacity while managing power consumption. It extends Rambus' portfolio of power management and memory interface products for LPDDR-based server memory. As AI training and inference workloads expand, data center operators are increasingly focused on improving computing output relative to energy consumption. For AI systems, this includes maximizing tokens processed per watt, a measure of energy efficiency that is becoming important as inference services and agentic AI applications scale. LPDDR6 SOCAMM2 is under development and represents the next stage in applying low-power double data rate memory technology to server platforms. The modular architecture is designed to combine LPDDR's power-efficiency characteristics with a compact, serviceable memory form factor suited to demanding AI workloads. Rami Sethi, senior vice president and general manager of Memory Interface Chips at Rambus, said the new PMIC builds on the company's server-memory power management technology and is intended to support memory architectures optimized for performance and energy efficiency. Micron Technology also highlighted the role of low-power memory in future AI infrastructure. Praveen Vaidyanathan, vice president and general manager of Cloud Memory Products at Micron, said LPDRAM is becoming increasingly important as AI systems place greater demands on memory capacity, bandwidth and power efficiency. He added that Micron continues to work with industry partners on standards such as SOCAMM2. Power management for LPDDR6 modules. The PMIC is designed to regulate the power supplied to LPDDR6 DRAM and other active components on a SOCAMM2 module. It converts the system supply voltage into the levels required by the memory and supporting chips. Alongside power conversion, the device is designed to support power sequencing, telemetry and fault protection. These functions help manage changing electrical demands, monitor operating conditions and protect module components against power-related faults. Rambus said the PMIC and its LPDDR6 SOCAMM2 serial presence detect (SPD) Hub are being developed to provide precise, module-level power management for future AI systems. The SPD Hub supports module configuration and related management functions, complementing the PMIC's power delivery capabilities. Together, the components are intended to support the performance, reliability and energy efficiency requirements of next-generation accelerated computing platforms. Extending Rambus' server memory portfolio. Rambus supplies memory interface chipsets for DDR- and LPDDR-based modules. Its portfolio includes registering clock drivers, PMICs, voltage regulators, SPD Hubs and temperature sensors. The company already offers an LPDDR5X SOCAMM2 chipset designed to provide power delivery, configuration and telemetry functions for current-generation SOCAMM2 modules. The new PMIC and SPD Hub extend that product roadmap to the developing LPDDR6 standard. The expansion reflects efforts across the semiconductor industry to develop memory architectures that can meet AI systems' growing requirements without proportionally increasing power consumption. Memory performance and energy efficiency are important considerations in accelerated computing, where processors must access large volumes of data to sustain high utilization. Rambus did not disclose pricing, sampling schedules or commercial availability timelines for the new PMIC. The product's adoption will depend on the development of LPDDR6 SOCAMM2, ecosystem integration and the requirements of future server platforms.

MarketScreener
Oct 13th, 2026
Rambus advances power-efficient AI infrastructure with industry-leading PMIC designed for LPDDR6 SOCAMM2.

Rambus advances power-efficient AI infrastructure with industry-leading PMIC designed for LPDDR6 SOCAMM2. New PMIC expands the Rambus family of LPDDR-based server module solutions and builds on the company's leadership in advanced server-memory power management Designed to enable upcoming low-power, high-performance LPDDR6 SOCAMM2 Delivers enhanced power efficiency to scale tokens per watt for AI workloads Architected in technical cooperation with customers and ecosystem partners to advance future-generation accelerated AI infrastructure Published on 10/13/2026 at 05:00 pm EDT Business Wire Rambus Inc. (NASDAQ: RMBS), a premier chip and silicon IP provider making data faster and safer, today announced an industry-leading Power Management IC (PMIC) designed to enable low-power, high-performance LPDDR6 Small Outline Compression Attached Memory Modules (SOCAMM2). Developed in technical cooperation with customers and ecosystem partners to support future-generation accelerated AI infrastructure, the PMIC expands the Rambus family of LPDDR-based server module chips and extends Rambus leadership in advanced server memory products. As AI training and inference workloads scale, the need for higher throughput within a given power envelope, measured in tokens per watt, is a critical consideration for AI infrastructure. This is driving demand for purpose-built memory solutions optimized for power efficiency, form factor and scalability. SOCAMM2 brings the power and performance benefits of LPDDR technology to a compact, modular and serviceable server-memory architecture designed for demanding AI systems. LPDDR6 SOCAMM2, in development now, represents the next important evolution in LPDDR-based server memory technology. "Inference and agentic AI are driving exciting new opportunities for memory innovation across the data center," said Rami Sethi, senior vice president and general manager of Memory Interface Chips at Rambus. "Our new PMIC designed for LPDDR6 SOCAMM2 builds on our leadership in server-memory power management. Working closely with industry leaders in alignment with the broader AI ecosystem, we are helping enable the high-performance, power-efficient memory architectures that maximize tokens per watt for AI workloads." "As AI systems place growing demands on memory capacity, bandwidth and power efficiency, LPDRAM is becoming an increasingly important technology for next-generation AI infrastructure," said Praveen Vaidyanathan, vice president and general manager of Cloud Memory Products at Micron Technology. "Micron has helped pioneer low-power memory for the data center and continues to work closely with ecosystem partners to advance industry standards such as SOCAMM2. We welcome Rambus' continued investment in LPDDR6 power management solutions, which help strengthen the broader low-power memory ecosystem." Building on Rambus Server Memory Power Management Leadership Rambus provides complete memory interface chipsets for DDR- and LPDDR-based memory modules, including registering clock drivers (RCDs), PMICs, voltage regulators, SPD Hubs and temperature sensors. The company continues to advance its memory module chipset roadmaps for high-volume CPU-based servers while expanding its portfolio to address emerging memory architectures for accelerated AI infrastructure. Rambus offers a complete LPDDR5X SOCAMM2 chipset, which provides the power delivery, configuration and telemetry functions required by the current-generation SOCAMM2. Building on this chipset strategy, the new PMIC, along with the Rambus SPD Hub, extend the LPDDR-based module roadmap to support the evolving requirements of the upcoming LPDDR6 SOCAMM2. Optimized for the dynamic workload conditions of future AI systems, the PMIC and SPD Hub designed for LPDDR6 SOCAMM2 provide efficient and precise module-level power management, including advanced power conversion, sequencing, telemetry and fault protection. The PMIC efficiently steps down the system voltage supply to the voltage levels needed to power the LPDDR6 DRAM and all other active chips on the module. These capabilities help support the performance, reliability and power efficiency required for next-generation accelerated computing platforms. Availability The Rambus PMIC designed for LPDDR6 SOCAMM2 is currently sampling to lead customers. More Information: Follow Rambus: Company website: rambus.com Rambus blog: rambus.com/blog LinkedIn: www.linkedin.com/company/rambus About Rambus Inc. Rambus delivers industry-leading chips and silicon IP for the data center and AI infrastructure. With over three decades of advanced semiconductor experience, our products and technologies address the critical bottlenecks between memory and processing to accelerate data-intensive workloads. By enabling greater bandwidth, efficiency and security across next generation computing platforms, we make data faster and safer. For more information, visit rambus.com. Forward-looking statements Information set forth in this press release, including statements as to Rambus' outlook and financial estimates and statements as to the expected timing and effects of Rambus products, constitute forward-looking statements within the meaning of the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. These statements are based on various assumptions and the current expectations of the management of Rambus and may not be accurate because of risks and uncertainties surrounding these assumptions and expectations. Factors listed below, as well as other factors, may cause actual results to differ significantly from these forward-looking statements. There is no guarantee that any of the events anticipated by these forward-looking statements will occur, or what effect they will have on the operations or financial condition of Rambus. Forward-looking statements included herein are made as of the date hereof, and Rambus undertakes no obligation to publicly update or revise any forward-looking statement unless required to do so by federal securities laws. Major risks, uncertainties and assumptions include, but are not limited to: any statements regarding anticipated operational and financial results; any statements of expectation or belief; other factors described under "Risk Factors" in Rambus' Annual Report on Form 10-K and Quarterly Reports on Form 10-Q; and any statements of assumptions underlying any of the foregoing. It is not possible to predict or identify all such factors. Consequently, while the list of factors presented here is considered representative, no such list should be considered to be a complete statement of all potential risks and uncertainties. View source version on businesswire.com: https://www.businesswire.com/news/home/20261013691270/en/ (C) Business Wire - 2026

FinancialContent
Oct 13th, 2026
Rambus advances power-efficient AI infrastructure with industry-leading PMIC designed for LPDDR6 SOCAMM2.

Rambus advances power-efficient AI infrastructure with industry-leading PMIC designed for LPDDR6 SOCAMM2. October 13, 2026 at 17:00 PM EDT i This article is third-party content and does not represent the views of this site. Tamar Securities, LLC make no guarantees regarding its accuracy or completeness. New PMIC expands the Rambus family of LPDDR-based server module solutions and builds on the company's leadership in advanced server-memory power management * Designed to enable upcoming low-power, high-performance LPDDR6 SOCAMM2 * Delivers enhanced power efficiency to scale tokens per watt for AI workloads * Architected in technical cooperation with customers and ecosystem partners to advance future-generation accelerated AI infrastructure Rambus Inc. (NASDAQ: RMBS), a premier chip and silicon IP provider making data faster and safer, today announced an industry-leading Power Management IC (PMIC) designed to enable low-power, high-performance LPDDR6 Small Outline Compression Attached Memory Modules (SOCAMM2). Developed in technical cooperation with customers and ecosystem partners to support future-generation accelerated AI infrastructure, the PMIC expands the Rambus family of LPDDR-based server module chips and extends Rambus leadership in advanced server memory products. As AI training and inference workloads scale, the need for higher throughput within a given power envelope, measured in tokens per watt, is a critical consideration for AI infrastructure. This is driving demand for purpose-built memory solutions optimized for power efficiency, form factor and scalability. SOCAMM2 brings the power and performance benefits of LPDDR technology to a compact, modular and serviceable server-memory architecture designed for demanding AI systems. LPDDR6 SOCAMM2, in development now, represents the next important evolution in LPDDR-based server memory technology. "Inference and agentic AI are driving exciting new opportunities for memory innovation across the data center," said Rami Sethi, senior vice president and general manager of Memory Interface Chips at Rambus. "Our new PMIC designed for LPDDR6 SOCAMM2 builds on our leadership in server-memory power management. Working closely with industry leaders in alignment with the broader AI ecosystem, we are helping enable the high-performance, power-efficient memory architectures that maximize tokens per watt for AI workloads." "As AI systems place growing demands on memory capacity, bandwidth and power efficiency, LPDRAM is becoming an increasingly important technology for next-generation AI infrastructure," said Praveen Vaidyanathan, vice president and general manager of Cloud Memory Products at Micron Technology. "Micron has helped pioneer low-power memory for the data center and continues to work closely with ecosystem partners to advance industry standards such as SOCAMM2. We welcome Rambus' continued investment in LPDDR6 power management solutions, which help strengthen the broader low-power memory ecosystem." Building on Rambus Server Memory Power Management Leadership Rambus provides complete memory interface chipsets for DDR- and LPDDR-based memory modules, including registering clock drivers (RCDs), PMICs, voltage regulators, SPD Hubs and temperature sensors. The company continues to advance its memory module chipset roadmaps for high-volume CPU-based servers while expanding its portfolio to address emerging memory architectures for accelerated AI infrastructure. Rambus offers a complete LPDDR5X SOCAMM2 chipset, which provides the power delivery, configuration and telemetry functions required by the current-generation SOCAMM2. Building on this chipset strategy, the new PMIC, along with the Rambus SPD Hub, extend the LPDDR-based module roadmap to support the evolving requirements of the upcoming LPDDR6 SOCAMM2. Optimized for the dynamic workload conditions of future AI systems, the PMIC and SPD Hub designed for LPDDR6 SOCAMM2 provide efficient and precise module-level power management, including advanced power conversion, sequencing, telemetry and fault protection. The PMIC efficiently steps down the system voltage supply to the voltage levels needed to power the LPDDR6 DRAM and all other active chips on the module. These capabilities help support the performance, reliability and power efficiency required for next-generation accelerated computing platforms. Availability The Rambus PMIC designed for LPDDR6 SOCAMM2 is currently sampling to lead customers. More Information: About Rambus Inc. Rambus delivers industry-leading chips and silicon IP for the data center and AI infrastructure. With over three decades of advanced semiconductor experience, its products and technologies address the critical bottlenecks between memory and processing to accelerate data-intensive workloads. By enabling greater bandwidth, efficiency and security across next generation computing platforms, Tamar Securities, LLC make data faster and safer. For more information, visit rambus.com. Forward-looking statements Information set forth in this press release, including statements as to Rambus' outlook and financial estimates and statements as to the expected timing and effects of Rambus products, constitute forward-looking statements within the meaning of the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. These statements are based on various assumptions and the current expectations of the management of Rambus and may not be accurate because of risks and uncertainties surrounding these assumptions and expectations. Factors listed below, as well as other factors, may cause actual results to differ significantly from these forward-looking statements. There is no guarantee that any of the events anticipated by these forward-looking statements will occur, or what effect they will have on the operations or financial condition of Rambus. Forward-looking statements included herein are made as of the date hereof, and Rambus undertakes no obligation to publicly update or revise any forward-looking statement unless required to do so by federal securities laws. Major risks, uncertainties and assumptions include, but are not limited to: any statements regarding anticipated operational and financial results; any statements of expectation or belief; other factors described under "Risk Factors" in Rambus' Annual Report on Form 10-K and Quarterly Reports on Form 10-Q; and any statements of assumptions underlying any of the foregoing. It is not possible to predict or identify all such factors. Consequently, while the list of factors presented here is considered representative, no such list should be considered to be a complete statement of all potential risks and uncertainties. Contacts. Press Contact: Cori Pasinetti Rambus Corporate Communications t: (650) 309-6226 [email protected] Report this content If you believe this article contains misleading, harmful, or spam content, please let Tamar Securities, LLC know.

Yahoo Finance
Oct 1st, 2026
Rambus could gain 30% revenue boost as AI agents drive server CPU market to $211B by 2030

Rambus could benefit significantly from the shift to AI agents, which are driving increased demand for server CPUs. Bank of America projects the server CPU market will grow from $61 billion this year to $211 billion by 2030, with the AI agent segment rising 14-fold. Rambus makes chips for server memory modules and holds a mid-40% share of the memory interface chip market. The company's next major opportunity is MRDIMM, a faster memory module with four times the interface chip content of standard DDR5 modules. Sales are expected to ramp in 2027 with new Intel and AMD platforms. Rambus estimates the MRDIMM market at $600 million. At current market share, this could add roughly $250 million annually to Rambus's existing $800 million revenue base, representing a 30% boost.