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Quest Global

Engineering services, digital transformation, asset management

Static Timing Analysis Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-time$160k - $220k

About the Job

Requirements

  • Expertise in synthesis, equivalency checking, and static timing analysis.
  • Experience with block-level and multi-voltage timing closure; full-chip (top-level) timing closure experience is also required elsewhere in the posting.
  • Experience using Synopsys DC/FC for synthesis, Synopsys Formality for equivalency checking, and Synopsys PrimeTime for static timing analysis.
  • Experience with high-complexity silicon in advanced technology nodes.
  • Familiarity with timing constraint development for hierarchical designs.
  • Knowledge of clock tree planning and implementation for SoCs.
  • Experience with timing engineering change order creation and final timing signoff.
  • Proficiency with static timing analysis tools such as PrimeTime, TCM, and Tempus, and scripting languages such as Tcl and Perl.
  • Proficiency with the Genus synthesis tool.
  • Ability to debug and fix timing issues and perform synthesis, equivalency checking, and static timing analysis.
  • Strong understanding of timing constraints, exceptions, clock tree synthesis, clock constraints, and multi-mode multi-corner timing closure.
  • Strong understanding of ASIC design flows, including RTL and place-and-route.
  • Bachelor's degree and 8+ years of related experience, or a Master's degree and 6+ years of related experience, or a PhD and 3+ years of related experience.
  • Ability to commute to and from the on-site location using personal transportation to meet required working hours.

Responsibilities

  • Develop and validate timing constraints for intricate SoC designs.
  • Define and implement timing signoff methodologies, including process corners, derates, and uncertainties.
  • Conduct pre-route timing checks and quality-of-results analysis.
  • Automate timing analysis processes using scripting languages such as Tcl or Perl.
  • Provide guidance on clock tree synthesis and optimization for energy-efficient designs.
  • Ensure compliance with timing signoff checklists and criteria.

Desired Qualifications

  • Top-level timing closure experience.
  • Post-graduate coursework.

About the Company

Quest Global

Engineering services, digital transformation, asset management

QuEST Global provides engineering and lifecycle services across aerospace, automotive, energy, healthcare, and transportation, focusing on digital transformation and asset management. It uses edge computing, cloud, AI/ML, and industrial IoT to deliver tailored engineering solutions through long-term partnerships, service contracts, project-based engagements, and strategic collaborations. It differentiates itself with a broad industry footprint, global delivery model, and emphasis on partnerships, talent development, and workplace culture. Its goal is to help clients improve operational efficiency and drive business growth by transforming engineering processes and assets with digital tools and data-driven management.

Company size
10,001+
Company stage
Growth Equity (Venture Capital)
Total funding
$581M
Headquarters
Greenville, SC
Founded
1997

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