Envision Employment Solutions

Senior Physical Design Engineer - Floorplan & PnR

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-timeNew Cairo City, Cairo Governorate, EgyptNo salary listedIn-person

About the Job

Requirements

At least 10 years of RTL-to-GDSII experience on 10nm-or-below nodes, working with designs of 500,000 to over 1 million instances.
Power-user proficiency with Synopsys and/or Cadence place-and-route tools, including ICC2, Fusion Compiler, and Innovus.
Strong floorplanning, power planning, clock tree synthesis, placement, routing, and timing-closure skills.
Strong analysis and issue-resolution skills for electromigration/IR drop, design-rule checking, layout-versus-schematic, and electrical-rule checking.
Knowledge of synthesis and design-for-test scan insertion.
Proficiency in Tcl, Perl, Python, and Makefile.
Tapeout experience.

Responsibilities

Own block- and full-chip floorplanning, partitioning, pin assignment, and power mesh design.
Run placement, clock tree synthesis, routing, and optimization to meet power, performance, and area targets.
Drive clock tree planning and analysis, and scan reordering.
Complete physical verification, including design-rule checking, layout-versus-schematic, antenna, and electrical-rule checking.
Resolve electromigration/IR drop issues and contribute to low-power implementation.
Work closely with static timing analysis, design-for-test, and RTL teams through signoff.
Complete multiple design cycles with little supervision.

Desired Qualifications

Top-level floorplanning experience is a plus.

Senior Physical Design Engineer (Floorplan & PnR)

Envision Employment Solutions · New Cairo City, Egypt · Full-time · Posted 2026-09-26

Workplace: on_site

Department: Semiconductor Engineering

Description

Envision Employment Solutions is currently looking for a Senior Physical Design Engineer (Floorplan & PnR) for one of our partners, an IT Services and IT Consulting company.

THE ROLE

A good floorplan makes every stage that follows easier, and a bad one haunts the project to tapeout. You'll own the implementation side of physical design, from partitioning and power planning through placement, CTS and routing, on some of the most advanced technology nodes out there.

WHAT YOU'LL DO

Own floorplanning, partitioning, pin assignment and power mesh design at block and full chip level
Run placement, CTS, routing and optimisation to close PPA targets
Drive clock tree planning and analysis, and scan reordering
Close physical verification: DRC, LVS, antenna, ERC
Resolve EM/IR issues and contribute to low power implementation
Work closely with STA, DFT and RTL teams through to signoff
Complete multiple design cycles with little supervision

WHAT WE'RE LOOKING FOR

10+ years of RTL to GDSII experience on 10nm or below nodes, with designs of 500k to 1M+ instances
Power user of PnR tools from Synopsys and/or Cadence (ICC2, Fusion Compiler, Innovus)
Excellent floorplan, power plan, CTS, place, route and timing closure skills
Strong EM/IR, DRC, LVS and ERC analysis and fixing
Good knowledge of synthesis and DFT scan insertion
Proficiency in Tcl, Perl, Python and Makefile
Tapeout experience; top level floorplanning is a plus

YOU'LL THRIVE HERE IF YOU

You can look at a floorplan and see the congestion before the tool does
You enjoy the puzzle of balancing power, performance and area
You work well on your own and still keep the wider team in the loop
You take pride in a clean DRC and LVS run
You want to work at the leading edge of process technology

Apply

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About the Company

Envision Employment Solutions

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