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Synopsys

EDA software for chip design

Applications Engineering Senior Engineer

Solution EngineeringConfirmed live in the last 24 hours
Full-timeBengaluru, Karnataka, IndiaNo salary listed

About the Job

Requirements

  • A BE, BTech, ME, or MTech in Electronics Engineering, Computer Science, or Microelectronics, with 3–5 years of hands-on industry experience in ASIC design or verification.
  • Deep working knowledge of low-power verification, including power estimation, reduction techniques, power exploration, audit, efficiency analysis, power-load models, memory power analysis, low-power simulation, low-power linting, and hardware/emulation cycle-based power profiling and correlation.
  • Proven experience with Synopsys low-power tools such as PrimePower-RTL (logical and physical mode), SpyGlass-Power, VC LP, PTPX/PrimePower, or RTL Architect (PPA), or equivalent industry-standard low-power signoff tools.
  • Strong command of VHDL, Verilog, and SystemVerilog RTL, and a solid understanding of ASIC design flows from RTL to tapeout.
  • Hands-on experience debugging power reports and matrices at RTL and netlist levels, and working with UPF for low-power verification.
  • Advanced scripting skills in TCL, Unix shell, Perl, or Python for automation, flow development, and debugging.
  • Ability to assess customer power-verification flow issues and propose concrete next steps.
  • Ability to explain complex power-correlation issues to design managers and R&D engineers, adjusting explanations to the audience.
  • Ability to manage multiple customer engagements with different tools, flows, and timelines.
  • Ability to work across time zones, teams, and functions and coordinate the right stakeholders.
  • Ability to challenge technically unsound customer requests constructively.

Responsibilities

  • Partner with semiconductor companies across the region to solve low-power verification challenges, including power estimation, reduction, audit, correlation, and efficiency analysis.
  • Deploy and optimize Synopsys low-power tools, including PrimePower-RTL, SpyGlass-Power, VC LP, and PTPX, across customer design flows at RTL and netlist levels.
  • Debug power reports, analyze power matrices, and trace issues through UPF, RTL, and gate-level designs to resolve discrepancies and improve accuracy.
  • Collaborate with Synopsys R&D and product validation teams to develop methodologies for customer-specific problems and provide real-world requirements for product roadmaps.
  • Build and maintain automation scripts in TCL, Perl, and Unix shell to streamline power-analysis workflows and improve customer-engagement turnaround time.
  • Coordinate with technical account managers and worldwide account teams to shape customer strategies, drive tool adoption, and support project completion.
  • Gather, refine, and track flow requirements based on customer feedback, engineering judgment, and tool capabilities.
  • Enable customers to meet power budgets and schedules by resolving power-verification bottlenecks.
  • Build repeatable, scalable low-power methodologies for customer verification across projects and product lines.
  • Support customer adoption of Synopsys solutions and long-term account relationships.
  • Catch power issues earlier in the flow to reduce customer design respins.
  • Serve as a technical advisor to design teams on power verification.
  • Support customer design teams in optimizing power for AI, mobile, and automotive chips.
  • Work with R&D, product validation, technical account managers, and global applications engineering teams to drive methodologies, solve customer problems, and enable project outcomes.

Desired Qualifications

  • Experience with glitch power analysis and power correlation across RTL, gate-level, and emulation environments.

About the Company

Synopsys

EDA software for chip design

Synopsys provides software tools and services for electronic design automation (EDA), helping engineers design, simulate, verify, and optimize semiconductor chips and systems. Its products cover the full design flow, including RTL-to-gating synthesis, place-and-route, timing analysis, verification, and silicon validation, as well as software integrity solutions and hardware-assisted verification. Engineers use these tools to model, simulate, and validate complex chip designs before manufacturing, reducing bugs and improving performance. Compared with many competitors, Synopsys differentiates itself through its broad, end-to-end design toolchain, large ecosystem of IP and integration with simulation and modeling capabilities gained from its 2025 merger with ANSYS, and its global scale and support. The company aims to help designers push the boundaries of chip and system performance, accelerate time-to-market, and enable silicon-to-systems design across a wide range of industries.

Company size
10,001+
Company stage
IPO
Headquarters
Sunnyvale, CA
Founded
1986

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