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Synopsys

EDA software for chip design

ASIC Physical Design Senior to Staff Engineer

Silicon & ASIC DesignPosted on Nov 12
Full-timeNo salary listedIn-person

About the Job

Requirements

  • A Bachelor of Engineering or Master of Science in Electrical Engineering is required, along with at least 2 years of direct physical design experience.
  • Proficiency in the full design cycle from RTL to GDSII, with a focus on physical design.
  • Solid engineering understanding of IC design, implementation flows, and methodologies for deep submicron design.
  • Advanced place-and-route and sign-off skills, including static timing analysis, physical verification, and electromigration and IR-drop analysis, to validate design robustness.
  • Ability to solve complex problems and attention to detail.
  • Ability to work proactively and independently with minimal supervision.
  • Ability to communicate effectively and influence and collaborate with cross-functional teams.
  • Ability to evaluate complex issues and provide innovative solutions.

Responsibilities

  • Lead the physical implementation of high-speed interface IPs from RTL to GDS, ensuring timing and physical sign-off.
  • Collaborate with cross-functional teams to integrate and verify IP designs to achieve project goals.
  • Provide technical guidance and mentorship.
  • Continuously improve design methodologies and processes to enhance efficiency and quality.
  • Develop high-performance physical IP and ensure the reliability and efficiency of physical design solutions.
  • Share technical expertise to elevate team capabilities.
  • Support the adoption and usability of products by providing engineering expertise.

About the Company

Synopsys

EDA software for chip design

Synopsys provides software tools and services for electronic design automation (EDA), helping engineers design, simulate, verify, and optimize semiconductor chips and systems. Its products cover the full design flow, including RTL-to-gating synthesis, place-and-route, timing analysis, verification, and silicon validation, as well as software integrity solutions and hardware-assisted verification. Engineers use these tools to model, simulate, and validate complex chip designs before manufacturing, reducing bugs and improving performance. Compared with many competitors, Synopsys differentiates itself through its broad, end-to-end design toolchain, large ecosystem of IP and integration with simulation and modeling capabilities gained from its 2025 merger with ANSYS, and its global scale and support. The company aims to help designers push the boundaries of chip and system performance, accelerate time-to-market, and enable silicon-to-systems design across a wide range of industries.

Company size
10,001+
Company stage
IPO
Headquarters
Sunnyvale, CA
Founded
1986

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