Ultra-Low Latency Network Architect

Hudson River Trading (HRT) is seeking an Ultra-Low Latency Network Architect to build, test, and optimize our global high-frequency trading infrastructure. In this role, you will lead hardware evaluation and lab benchmarking while leveraging Python and data analysis techniques to analyze high-volume PCAP captures, telemetry streams, and tick-to-trade latency distributions. You will bridge low-level network engineering with performance engineering teams to reduce jitter and push network performance into the single nanosecond domain. 

Responsibilities

• Hardware Evaluation & Lab Testing: Establish and run a dedicated network testing lab. Design automated benchmark frameworks using traffic generators (Spirent/Ixia) to simulate, measure and validate various protocols at a network level and to stress-test  SmartNICs, switches, FPGAs, and transceivers
• Network Data Analysis & Telemetry Pipeline: Build custom Python pipelines to process, analyze, and visualize high-volume packet captures (PCAPs), queue depth metrics, and telemetry data from FPGA/Corvil appliances to pinpoint anomalies. Write tools to automate lab testing procedures, parse binary network logs, and generate latency-distribution reports (e.g., 99.99th percentile jitter analysis)
• HFT Architecture & Co-location: Architect and maintain low latency trading networks across global exchange colocation sites. Optimize trading network signals over wireless low-latency backhaul networks
• Kernel Bypass & Acceleration: Familiarity with kernel-bypass stacks (AMD/Solarflare Onload/DPDK), hardware accelerator cards and layer-1/2 FPGA switches to minimize execution overhead. Collaborate with hardware engineering teams to benchmark performance for embedded network components such as network adapters and/or network co-processors
• Time Synchronization: Oversee PTP (IEEE 1588v2) and White Rabbit time synchronisation systems
• Routing and Switching: Design and maintain large-scale L2/L3 architectures specifically fine-tuning BGP, OSPF and PIM-SSM/IGMP multicast trees for sub-microsecond convergence and resilient market data delivery
• Maintain Industry Awareness: Stay current with emerging low-latency networking technologies, including new SmartNICs, FPGA acceleration, and high-speed transceivers. Evaluate and recommend new hardware and software solutions to improve network performance

Qualifications

• 10+ years designing and operating ultra-low latency networks within HFT, market making, or quantitative fund environments. Knowledge of exchange colocation, market data feeds, and order routing protocols (FIX, OUCH, ITCH) is essential
• Advanced Python skills using libraries like pandas, numpy, or pyarrow to parse large PCAP datasets, analyze time-series telemetry, and calculate microsecond/nanosecond statistics
• Hands-on experience building network testing labs, using hardware traffic generators (Spirent/Ixia) and packet capture tools
• Expertise with Arista (7130 series), Cisco (Nexus 3550/3548), LDA L1 switches, AMD Solarflare, and NVIDIA Mellanox hardware. Familiarity with FPGA driven low latency applications or custom accelerator cards  in the context of high performance trading environments
• Deep knowledge of BGP/OSPF, Linux network stack tuning, PTP (IEEE 1588), White Rabbit, PIM-SSM multicast, and large scale L2/L3 topologies. Awareness and experience with AI inference networks is a plus but not required
• Proficiency with Ansible, SQL and Python network automation tools (e.g., Scapy, Netmiko, or AsyncIO) for config generation and orchestration. Experience with observability stacks such as Victoriametrics, Prometheus, Grafana, and Docker 

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.