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Synopsys

EDA software for chip design

Applications Engineering Senior Staff Engineer

Implementation & Technical Account ManagementConfirmed live in the last 24 hours
Full-timeBengaluru, Karnataka, IndiaNo salary listedIn-person

About the Job

Requirements

  • At least 10 years of hands-on ASIC design or application engineering experience, with deep expertise in physical implementation including placement, optimization, clock tree synthesis, and routing.
  • Expert-level knowledge of Synopsys backend tools, specifically Fusion Compiler and ICC2, including logical and physical synthesis, timing closure techniques, macro placement, and routing at advanced nodes.
  • Strong working knowledge of the RTL-to-GDS full flow, with the ability to debug issues from synthesis through signoff and explain root causes to customers and R&D.
  • Demonstrated experience working directly with customers or cross-functional engineering teams to solve complex technical problems under tight schedules and high stakes.
  • Deep understanding of advanced-node design challenges at 5nm and below and the methodologies required to achieve timing, power, and area targets at scale.
  • A bachelor's or master's degree in Electrical Engineering or Computer Engineering, or equivalent practical experience.

Responsibilities

  • Deploy Fusion Compiler and ICC2 on customer designs at advanced nodes, solving power, performance, and area challenges using machine-learning placement, physical synthesis, and multi-source clock tree synthesis techniques.
  • Work directly with customers to develop, debug, and optimize RTL-to-GDS implementation flows, identifying design bottlenecks and tool behavior that blocks timing closure or violates power budgets.
  • Run competitive benchmarks of Synopsys implementation solutions against rival tools, document quality-of-results improvements, and build technical narratives for customer evaluations.
  • Translate customer findings into actionable requirements for Synopsys research and development, driving tool enhancements for immediate design challenges and long-term methodology gaps.
  • Lead customer migrations to new electronic design automation tool versions by validating flows, identifying regressions, ensuring power, performance, and area gains carry through to production designs, and supporting adoption.
  • Represent customer needs to Synopsys research and development and explain product capabilities to customers.
  • Identify recurring customer pain points and develop reusable solutions, scripts, or methodologies that scale across designs and customers and influence product direction.

Desired Qualifications

  • Experience with static timing analysis tools such as PrimeTime is a strong plus.
  • Familiarity with front-end synthesis flows in Design Compiler or Fusion Compiler is a strong plus.

About the Company

Synopsys

EDA software for chip design

Synopsys provides software tools and services for electronic design automation (EDA), helping engineers design, simulate, verify, and optimize semiconductor chips and systems. Its products cover the full design flow, including RTL-to-gating synthesis, place-and-route, timing analysis, verification, and silicon validation, as well as software integrity solutions and hardware-assisted verification. Engineers use these tools to model, simulate, and validate complex chip designs before manufacturing, reducing bugs and improving performance. Compared with many competitors, Synopsys differentiates itself through its broad, end-to-end design toolchain, large ecosystem of IP and integration with simulation and modeling capabilities gained from its 2025 merger with ANSYS, and its global scale and support. The company aims to help designers push the boundaries of chip and system performance, accelerate time-to-market, and enable silicon-to-systems design across a wide range of industries.

Company size
10,001+
Company stage
IPO
Headquarters
Sunnyvale, CA
Founded
1986

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