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Astera Labs

Designs chips that connect data center systems

Technical Lead Digital Design Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeSan Jose, CA, USA$160k - $200kIn-person

About the Job

Requirements

  • A bachelor's degree in electrical engineering or equivalent is required.
  • At least 5 years of experience developing SoC or silicon products in the server, storage, and/or networking markets is required.
  • Expertise in RTL coding with SystemVerilog and synthesis using Synopsys or Cadence is required.
  • A track record of delivering high-quality digital designs from definition to production is required.
  • Experience in high-speed design in advanced technology nodes is required.
  • Understanding of functional and formal verification at block and chip level is required.
  • Understanding of clocking, clock-domain crossing, reset-domain crossing, and static-timing analysis is required.
  • Proficiency with high-speed protocols such as PCIe, Ethernet, DDR, or similar is required.
  • Experience with IP development and integration is required.
  • Expertise in design methodology, CAD automation, or design infrastructure is required.
  • Proven SystemVerilog and Python expertise in a production environment is required.
  • Familiarity with Synopsys and/or Cadence digital design flows is required.
  • A basic understanding of UVM-based verification methodologies is required.
  • The candidate must be able to balance multiple priorities in a dynamic environment.
  • The candidate must be comfortable collaborating cross-functionally with global teams.
  • The candidate must adapt quickly to changing requirements and work independently to deliver high-quality designs.

Responsibilities

  • Own RTL implementation of complex digital designs from micro-architecture through sign-off.
  • Collaborate with verification teams to review test plans and debug issues.
  • Support efforts to achieve timing closure and implement Design-for-Test features.
  • Develop scripting and automation to improve ASIC methodology.
  • Be accountable for design quality and overall design success, with support from senior engineers.

Desired Qualifications

  • Experience with embedded firmware development or standard embedded processor subsystems such as RISC-V or Arm is a plus.
  • Knowledge of Design-for-Test in a production environment is preferred.

About the Company

Astera Labs

Designs chips that connect data center systems

Astera Labs designs chips and hardware modules that move data between processors, memory and accelerators in data centers. Its customers include cloud providers, chip vendors and equipment makers building servers and large computing clusters for AI and other workloads. Retimers restore signal quality, switches connect devices and memory controllers expand the memory available to computing systems, while COSMOS software monitors and manages these links. The company sells its products directly and through distributors, using outside manufacturers to fabricate and assemble its hardware. Astera Labs was founded in 2017 and is headquartered in San Jose, California.

Company size
501-1,000
Company stage
IPO
Headquarters
San Jose, CA
Founded
2017

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