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Micron Technology

Makes memory and storage chips for AI and PCs

Master ASIC Device Technology & Silicon Yield Engineering

Hardware Validation & TestingConfirmed live in the last 24 hours
Full-timeHyderabad, Telangana, IndiaNo salary listedIn-person

About the Job

Requirements

  • A Ph.D. or M.S. in Electrical Engineering, Materials Science, Physics, Semiconductor Engineering, or equivalent experience.
  • At least 12 years of semiconductor industry experience.
  • Strong background in advanced CMOS technology and silicon product development.
  • Proven success leading yield improvement, RMA, and failure analysis efforts.
  • Experience working directly with foundries and OSAT partners.
  • Deep understanding of CMOS device physics and advanced semiconductor process technologies.
  • Strong expertise in SRAM architecture, memory design fundamentals, memory margin analysis, and failure mechanisms.
  • Strong understanding of high-speed interface technologies, including PCIe, ONFI, LPDDR, SerDes, and clocking architectures.
  • Experience with post-silicon debug and characterization of complex ASIC devices.
  • Expertise in process-design interaction analysis and variation-aware design methodologies.
  • Strong knowledge of signal integrity, power integrity, timing closure methodologies, device variability and mismatch analysis, and reliability-induced failure mechanisms.
  • Experience correlating Wafer Acceptance Test (WAT), electrical test, yield, reliability, and failure analysis data, as well as customer-return information.

Responsibilities

  • Lead end-to-end investigations of silicon yield loss, field returns, customer escalations, and reliability failures.
  • Drive root-cause analysis for complex silicon issues spanning process, design, test, package, and system interactions.
  • Develop hypothesis-driven debug strategies and coordinate multi-functional execution.
  • Own resolution of critical yield and quality issues through containment, corrective actions, and prevention plans.
  • Analyze device-level failure mechanisms and process sensitivities affecting ASIC functionality and yield.
  • Evaluate design-process interactions affecting analog, mixed-signal, memory, high-speed I/O, and PCIe PHY performance.
  • Partner with foundry teams to understand process variations, excursions, reliability risks, and technology limitations.
  • Translate silicon learning into actionable design and process improvements.
  • Lead root-cause investigations involving design-process interactions affecting SRAM, PCIe PHY, ONFI interfaces, SerDes, analog/mixed-signal circuits, and high-speed digital subsystems.
  • Analyze silicon failures across transistor, circuit, block, die, package, and system levels.
  • Drive post-silicon debug activities involving design teams, DFT, product engineering, quality, reliability, foundry, and customer support organizations.
  • Debug SRAM single-bit and multi-bit failures, read/write margin failures, timing and voltage sensitivity issues, PCIe PHY performance degradation, signal integrity and jitter-related failures, yield excursions linked to process variation, and field-return and RMA failures.
  • Develop silicon characterization plans to isolate process-, design-, and test-related contributors.
  • Drive silicon learning feedback into next-generation ASIC architecture and design methodologies.
  • Drive advanced failure analysis activities, including FIB, SEM/TEM, EFA, OBIRCH, LVP, emission microscopy, and physical cross-section analysis.
  • Correlate failure signatures with design, process, and manufacturing data.
  • Interpret failure analysis results and convert findings into clear engineering actions.
  • Lead technical reviews with Product Engineering, DFT, Design, Reliability, Quality, Operations, Foundry, and external partners.
  • Present complex technical findings to executive leadership.
  • Influence design and technology roadmaps to improve future product robustness and yield learning.

Desired Qualifications

  • Experience supporting SSD controller, AI accelerator, networking, or high-performance compute ASICs.
  • Expertise in PCIe PHY, SerDes, memory subsystem, or analog mixed-signal debug.
  • Track record resolving field-quality issues visible to executive leadership and customers.
  • Experience applying AI/ML tools for yield analytics, anomaly detection, and root-cause analysis acceleration.
  • Experience mentoring engineering teams and driving multi-site technical investigations.

About the Company

Micron Technology

Makes memory and storage chips for AI and PCs

Micron Technology designs and manufactures memory and storage chips, mainly DRAM and NAND flash, used in data centers, PCs, phones, cars and industrial equipment. It is one of only three companies that make HBM, the stacked high-bandwidth memory placed beside processors in AI servers, and it is the largest memory chipmaker based in the United States. Unlike chip designers that outsource production, Micron runs its own fabs and assembly sites in the United States and across Asia. It earns money by selling chips, memory modules and solid-state drives to cloud providers, device makers and distributors. Micron was founded in 1978 and is headquartered in Boise, Idaho.

Company size
10,001+
Company stage
IPO
Headquarters
Boise, ID
Founded
1978

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