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Rambus

Licenses high-speed chip-to-chip connectivity IP

Mixed-Signal Design Intern

Silicon & ASIC DesignPosted on Nov 13
InternshipSan Jose, CA, USAIn-person

About the Job

Requirements

  • Enrollment in a Master of Science or PhD program in Electrical Engineering and a minimum GPA of 3.5/4.0.
  • Coursework or experience in CMOS mixed-signal circuit design.
  • Knowledge of basic circuit and timing design principles.
  • Knowledge of Verilog-A and Verilog is desirable.
  • Ability to work with a diverse team.

Responsibilities

  • Design and simulate high-speed mixed-signal custom circuits.
  • Research and implement optimal low-power architecture.
  • Work with the layout team to achieve post-extraction performance.
  • Document analysis and simulation to demonstrate that the design achieves electrical and timing parameters and follows the pre-silicon verification flow.
  • Work under the supervision of senior design engineers on the team.

Desired Qualifications

  • Knowledge of Verilog-A and Verilog.

About the Company

Rambus

Licenses high-speed chip-to-chip connectivity IP

Rambus designs, develops, and licenses high-speed chip-to-chip connectivity technology. Its IP powers data center servers, AI accelerators, and automotive systems, and is licensed to other semiconductor companies rather than manufactured and sold directly. The products are high-speed interfaces and security features embedded in chips, enabling fast, reliable communication between components. Rambus differentiates itself through a licensing-based model focused on advanced IP for memory, security, and high-speed interfaces across data centers, AI, and automotive markets, rather than relying on a traditional product lineup. The company’s goal is to enable high-performance chip communication at scale by monetizing its intellectual property through licensing and expanding into growing markets like data centers, AI, and automotive.

Company size
1,001-5,000
Company stage
IPO
Headquarters
San Jose, CA
Founded
1990

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