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SiFive

Designs and sells RISC-V semiconductor cores

Staff Design Verification Engineer - High Performance CPU Core

Hardware Validation & TestingConfirmed live in the last 24 hours
Full-timeIn-person

About the Job

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • At least 7 years of relevant experience in ASIC, CPU/core, or system-on-chip design verification.
  • Strong hands-on experience with SystemVerilog and Universal Verification Methodology-based verification.
  • Direct experience with CPU/core verification and a strong understanding of computer architecture and CPU microarchitecture.
  • Experience in one or more high-performance CPU areas such as Frontend, Midcore, Load-Store Unit, memory ordering/consistency, or hardware prefetch verification.
  • Strong knowledge of verification-flow methodology, including test planning, constrained-random or directed stimulus generation, failure analysis, coverage analysis, and coverage closure.
  • Strong debugging skills and the ability to translate architectural intent into effective verification strategy and execution.
  • A Bachelor of Science or Master of Science degree in Electrical Engineering, Computer Engineering, or Computer Science.
  • At least 5 years of relevant experience with IP/component functional verification, preferably in core/CPU verification.
  • A deep understanding of computer architecture.
  • Experience developing with object-oriented programming principles.
  • Successful background and reference checks.
  • Satisfactory proof of the right to work in the United States of America.
  • Authorization to access export-controlled technology under applicable export-control laws, or the ability to obtain any necessary export license or approval.

Responsibilities

  • Own verification planning and execution for one or more high-performance out-of-order CPU core areas, with typical scope across Frontend, Midcore, Load-Store Unit, Hardware Prefetch, or related core-level interactions.
  • Drive block-level and core-level verification planning, debugging, coverage analysis, and closure for complex CPU features and microarchitectural behavior.
  • Define verification strategies for instruction fetch, branch prediction, issue and dispatch behavior, pipeline interactions, load/store ordering, hazard handling, memory consistency, and hardware prefetch correctness.
  • Develop and maintain verification environments, checkers, scoreboards, assertions, stimulus, and coverage models that expose corner cases and improve bug-finding efficiency.
  • Partner with architecture and design teams from early feature-definition stages to review specifications, identify ambiguity, and improve design debugability and verification quality.
  • Drive failure analysis and root-cause debugging across specifications, RTL, test content, and verification infrastructure.
  • Contribute reusable methodology, infrastructure, and technical guidance that improves productivity and verification quality across future core generations.

Desired Qualifications

  • Experience with out-of-order core verification.
  • Experience using formal verification and/or emulation for high-risk or performance-sensitive verification problems.
  • Experience collaborating with performance, compiler, system verification, and software teams to close verification gaps from multiple perspectives.
  • Experience mentoring engineers and influencing verification methodology beyond the immediate block or feature area.
  • Familiarity with Python, C, C++, or other scripting or programming languages used for design-verification infrastructure and automation.

About the Company

SiFive

Designs and sells RISC-V semiconductor cores

SiFive designs and sells RISC-V based processors and related IP for use in devices and systems. Its chips come as cores and system-on-chip designs built on the open RISC-V instruction set, enabling customers to integrate high-density, energy-efficient compute into products. Unlike competitors that rely on closed architectures, SiFive leverages openness to offer flexible, scalable, and cost-effective solutions that boost compute density. The company aims to grow the RISC-V ecosystem by delivering high-performance hardware that helps customers tackle data-heavy tasks and build smarter devices.

Company size
501-1,000
Company stage
Series G
Total funding
$772.5M
Headquarters
Santa Clara, CA
Founded
2015

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