Principal AI SoC Runtime Software Architect
Velaura
Principal AI SoC Runtime Software Architect
Velaura
Designs energy-efficient AI silicon and systems
Salary Range: 200000 to 300000 (Currency: USD) (Pay period: per-year-salary)
We are looking for a Principal AI SoC Runtime Software Architect to own the software architecture that turns Velaura’s heterogeneous AI SoC into a coherent, high-performance execution platform.
This role will define and lead development of the end-to-end runtime spanning sensor ingest, preprocessing, AI inference, postprocessing, and delivery of results to robotics and other physical and edge AI applications. The runtime will coordinate execution and data movement across the SoC’s CPU cores, AI accelerator, vision and multimedia engines, and other embedded processors. The complete runtime must coordinate heterogeneous workloads, manage ownership, synchronization, and safe reuse of shared data buffers, minimize data movement, provide predictable low-latency execution, recover from failures, and expose cohesive APIs and observability to applications and SDK components.
The ideal candidate combines deep runtime and systems-software expertise with a strong understanding of heterogeneous compute, Linux kernel and driver interfaces, DMA and shared-memory architectures, and performance-sensitive AI or multimedia pipelines. This will be a hands-on principal architect and technical lead who directs engineers across runtime, kernel, driver, firmware, multimedia, and SDK development.
Define the SoC-wide execution model for coordinating workloads across heterogeneous compute and media engines, including dependency management, resource arbitration, priority and QoS, and concurrent pipeline behavior.
Set the architecture and technical direction for the AI inference runtime, including compiled-model execution, integration with industry-standard AI execution frameworks, and interfaces to applications and the broader Velaura SDK.
Own the end-to-end dataflow architecture for sensor-to-application pipelines, ensuring that camera, media, preprocessing, inference, and postprocessing components operate as an efficient and coherent system.
Define the SoC-wide memory and buffer-sharing architecture across user space, the kernel, and heterogeneous hardware engines, establishing clear ownership, coherency, isolation, synchronization, and lifecycle semantics.
Define the division of responsibility and interface contracts among the runtime, kernel drivers, firmware, and hardware engines, including execution, completion, telemetry, fault management, and recovery semantics.
Partner with the compiler team to define the compiler–runtime contract, ensuring compiled artifacts contain the metadata and execution information needed for the runtime to load, validate, execute, profile, and maintain compatibility across releases.
Establish a system-wide observability and performance architecture that correlates behavior across software and hardware layers and enables optimization against latency, throughput, bandwidth, power, utilization, and predictability goals.
Define the runtime resilience and validation architecture, including fault-containment and recovery policies, architecture-level acceptance criteria, and qualification across correctness, concurrency, compatibility, performance, and sustained workloads.
Extensive experience designing and building production runtime systems, embedded middleware, multimedia frameworks, or other performance-critical systems software.
Strong C/C++ programming skills and demonstrated ability to architect and contribute hands-on to production runtime software spanning application-facing APIs, user-space libraries, and low-level driver, firmware, and hardware interfaces.
Strong understanding of heterogeneous and asynchronous execution, including command submission, queues, events, dependencies, synchronization, concurrency, scheduling, and resource management.
Strong understanding of device memory, DMA, IOMMU/SMMU, cache coherency, memory mapping, shared buffers, buffer lifetimes, and kernel/user-space memory interfaces.
Experience optimizing end-to-end data movement and execution across multiple hardware engines rather than focusing solely on individual kernels or accelerator performance.
Experience designing stable runtime APIs with well-defined compatibility, versioning, error handling, diagnostics, and recovery behavior.
Demonstrated ability to debug complex cross-layer correctness and performance problems using disciplined, data-driven methods, profiling, and tracing.
Demonstrated technical leadership across component and organizational boundaries, including translating system requirements into clear architectures, interfaces, implementation guidance, and validation strategies.
Direct experience developing or extending AI inference runtimes or execution providers, such as ONNX Runtime, TensorRT-like runtimes, OpenVINO, TensorFlow Lite delegates, Qualcomm QNN/SNPE, TVM runtimes, or comparable systems for NPUs, GPUs, DSPs, or other accelerators.
Linux kernel development or upstream contribution experience involving device, accelerator, media, or shared-memory subsystems.
Experience with robotics, autonomous systems, edge AI, ROS 2, camera pipelines, ISP integration, V4L2/media, GStreamer, or other sensor-driven workloads.
Familiarity with compiled-model artifacts, quantized execution, tensor layouts, graph partitioning, memory planning, and compiler/runtime integration.
Experience with embedded Linux SDKs, production deployment, long-term runtime/API compatibility, or the security and isolation requirements of multi-process accelerator systems.
Velaura is building next-generation compute technology for cloud, edge, and Physical AI. Our solutions will enable robots, autonomous systems, drones, and other intelligent machines to operate efficiently in the physical world.
This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape the future of Physical AI, we would love to hear from you.
Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment
opportunities to minorities, women, individuals with disabilities, and protected veterans.
Velaura is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or a reasonable accommodation for any part of the application or hiring process may contact us at: [email protected]. This contact
information is for accommodation requests only. Evaluation of requests for reasonable accommodation will be determined on a case-by-case basis.
Velaura AI designs and manufactures ultra-energy-efficient AI infrastructure, including 3nm ASIC chips, Teraflux mining systems, FluxVision fleet-management software, and AuraLinks rack-level networking. Customers deploy the hardware in data centers, while FluxVision monitors and manages fleets; EnergyTune and AutoTune dynamically adjust power to meet grid stability, and AuraLinks reduces bottlenecks in AI training and inference. The company differentiates itself with a team of silicon architects from Apple, Google, and Qualcomm, plus a patent-pending energy-management approach and a fully integrated hardware-software stack. Its goal is to enable massive AI deployment by delivering powerful, energy-efficient compute and networking that aligns with sustainable energy grids and domestically produced technology.
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