Internship

Design Engineering Intern

Cadence Design Systems

Cadence Design Systems

5,001-10,000 employees

Provides software, hardware, and IP for electronic system design

Hardware

Austin, TX, USA

Required Skills
Verilog
Requirements
  • BS/MS - Electrical/Electronics/VLSI
  • Strong background on Digital design and functional verification fundamentals
  • Exposure/expertise in System Verilog and UVM based functional verification environment development is required
  • Scripting knowledge will be a plus
Responsibilities
  • Functional verification of the DDR Memory Controller and Phy IP solution
  • Working with the existing functional verification environment
  • Addition of new features into the verification environment
  • Ensuring various customer configurations are clean as part of verification regressions
  • Supporting customers in case of any issues with using the verification environment
  • Ensuring that the design is in line with the technical and quality requirements set for the team
  • Helping to solve technical challenges

Cadence Design Systems

Cadence Design Systems

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Cadence Design Systems, a recognized leader in electronic systems design, leverages over three decades of computational software expertise to deliver comprehensive solutions, including software, hardware, and IP, that transform design ideas into tangible products. The company's Intelligent System Design strategy has made it a trusted partner for the world's leading companies in diverse markets such as hyperscale computing, 5G communications, automotive, and healthcare. Cadence's commitment to fostering a positive work environment is evident in its eight-year streak on Fortune's 100 Best Companies to Work For list, underscoring its industry leadership and competitive edge.

Company Stage

N/A

Total Funding

$462.8M

Headquarters

San Jose, California

Founded

1988

Growth & Insights
Headcount

6 month growth

1%

1 year growth

10%

2 year growth

16%
INACTIVE