SiTime

Fabless MEMS timing solutions provider

Senior Logic Design Engineer - Digital Design

Silicon & ASIC DesignUpdated on Nov 14

Full-timeRijswijk, NetherlandsIn-person

About the Job

Requirements

A Master’s degree in electrical engineering and 5 years of relevant industry experience are required.
Excellent verbal and written communication skills in English are required.
Proficiency in Verilog and SystemVerilog is required.
Expertise in digital logic design fundamentals, including clock divider circuits, multi-clock logic designs, clock-domain crossing, first-in-first-out designs, and finite-state machines, is required.
Experience designing mixed-signal digital logic is required.
A basic understanding of discrete-time signal processing theory and finite impulse response and infinite impulse response filter design is required.
Solid experience in digital design flow, including register-transfer-level design, synthesis, timing constraints, and static timing analysis, is required.
Skill in Perl, Tcl, or Python scripting languages is required.

Responsibilities

Develop micro-architecture specifications for logic circuits by reading and comprehending product requirement documents.
Develop register-transfer-level designs from micro-architecture specifications using Verilog or SystemVerilog as the hardware description language.
Develop standalone test benches to verify register-transfer-level behavior.
Write and verify SystemVerilog Assertions for designs.
Write timing constraints and clock definitions for synthesis and place-and-route tools.
Run industry-standard synthesis tools such as Genus or Design Compiler and resolve timing problems that arise.
Understand timing, area, and power design tradeoffs and improve them.
Read and interpret static timing analysis reports from industry-standard tools such as PrimeTime.
Interact and communicate cross-functionally with analog, verification, backend, system, and test engineering teams.
Perform post-silicon bring-up, validation, and debugging.

Desired Qualifications

A Ph.D. in electrical or computer engineering and 3 years of relevant industry experience.
2–5 years of experience designing high-precision digital arithmetic logic and digital signal processing.
2–5 years of experience designing digital phase-locked loops.
Experience in complex finite-state-machine design.
Familiarity with MATLAB, Simulink, or other high-level modeling tools.
Experience in low-power digital design flow.
A basic understanding of control theory.

About SiTime

SiTime Corporation is a precision timing company. Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 3 billion devices shipped, SiTime is changing the timing industry. For more information, visit www.sitime.com.

Job Summary

We at SiTime take pride in being the only company in the market that offers MEMS-based timing solutions. Our MEMS dies are uniquely complemented by our CMOS dies in the same package. We use state-of-the-art analog and digital circuits to achieve very aggressive design specs for our timing solutions. Our precision timing products keep pushing the boundaries of the industry across all dimensions and are by far superior to our competition. This has enabled us to continuously gain market share.

This has been achieved by pushing the innovation boundaries in MEMS and CMOS. Consisting of analog and digital blocks, our CMOS dies present unique technical challenges. The digital portion of our chips has been growing in the past few years and is expected to grow more rapidly in the upcoming years as our functionality and features scale up. To address our unique technical challenges, we are looking for a strong Senior Logic Design Engineer with a solid background in key digital design and implementation areas. It is not necessary to meet all job requirements to be a qualified candidate for the position.

Responsibilities:

Developing micro-architecture specification of the logic circuit from reading and comprehending the Product Requirement Document (PRD).
Developing the Register Transfer Level (RTL) design from the micro-architecture specification using Verilog or SystemVerilog as the HDL.
Developing standalone test benches to verify the RTL behavior.
Writing and verifying SystemVerilog Assertions (SVA) for a design.
Writing timing constraints and clock definition for synthesis and place and route tools.
Running industry-standard synthesis tools (e.g., Genus or Design Compiler) and being able to fix timing problems if they arise.
Understanding various design tradeoffs including timing/area/power and knowing how to improve them.
Reading and understanding the Static Timing Analysis (STA) reports from an industry-standard STA tool (e.g., Prime Time).
Cross-functional interactions and communication with various teams within SiTime including analog, verification, backend, system, and test engineering teams.
Post-Si bring-up, validation, and debugging.

Qualifications & Requirements:

Master’s degree in electrical engineering plus 5 years of relevant work experience in the industry.
Excellent verbal and written communication skills in English.
Proficient in Verilog and SystemVerilog.
Expertise in digital logic design fundamentals such as clock divider circuits, multi-clock logic designs, CDC, FIFO, FSM, etc.
Experience in designing mixed-signal digital logic.
Basic understanding of Discrete time Signal Processing theory, FIR, and IIR filter design.
Solid experience in digital design flow including RTL design, synthesis, timing constraints, and STA.
Skilled in scripting languages Perl/Tcl/Python.

Desired Characteristics & Attributes:

Ph.D. in electrical/computer engineering plus 3 years of relevant industry experience.
2-5 years of experience in designing high-precision digital arithmetic logic and Digital Signal Processing.
2-5 years of experience in designing Digital Phase-Locked Loops (DPLL).
Experience in complex FSM design.
Familiarity with MATLAB, Simulink, or any other high-level modeling tools.
Experience in low-power digital design flow.
Basic understanding of the Control Theory.

The actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.

SiTime compensation packages includes base salary, bonus based on achieving your innovation goals and equity.

Learn More about SiTime: Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique.

Pay Range

€57.420—€78.960 EUR

Pay Range 57420 - 78960 EUR

About the Company

SiTime

Fabless MEMS timing solutions provider

SiTime designs MEMS-based timing solutions (oscillators, network synchronizers, and jitter cleaners) as a fabless semiconductor company. MEMS resonators on silicon replace quartz to generate precise clocks and synchronize networks, with manufacturing handled by third-party foundries. The approach offers smaller size, lower power consumption, and better temperature stability, supported by scalable, design-focused development rather than in-house fabrication. Its goal is to expand MEMS timing adoption across automotive, industrial, IoT, mobile, aerospace, and telecom markets worldwide.

Company size: 501-1,000
Company stage: IPO
Headquarters: Santa Clara, CA
Founded: 2005

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