SMTS Silicon Design Engineer

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Job Role and Responsibility: AMD, Inc., is hiring SMTS Silicon Design Engineer to contribute to AMD’s CDFX DV team to perform the DFT IP verification, which includes work on IP level test plan creation and development, conducting and participating in test plan reviews. Develop scalable verification components, random-constrained stimulus, and debugging regression failures. Perform code reviews and DV coverage analysis. Provide technical guidance and innovative ideas to improve quality, processes, and productivity. Lead DV execution, including DV project planning, delivery timelines, deliverables, and quality checks. Track project progress and ensure projects stay on track for timely completion. Provide technical support to SOC teams (internal customers) on DFT IP deliverables and tape out readiness signoff. Collaborate with cross-functional DV technical leaders to drive DFX DV strategy.

Can work remotely.

Multiple openings.  Qualified applicants click “APPLY NOW” button to apply online.

Travel required: NO       

Qualifications: Degree required

Master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electrical and Electronics Engineering, or related field.

Qualifications: Amount and type of experience required: Four (4) years of experience in the job offered or closely related engineering role.

Alternate combination of education and experience: Employer will alternatively accept a Bachelor’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electrical and Electronics Engineering, or related field and six (6) years of progressive post-baccalaureate experience in the job offered or closely related engineering role.

Specific skills required: The following skills are required:

Position requires four (4) years of experience in the following:

• Design verification on complex CPU/ASIC projects from inception to tape-out;
• Functional design verification, including test bench architecture, tool integration, coverage, power domains, random constrained testing, and debug;
• Leading a small design verification engineering team;
• IP level test plan creation and development;
• Conducting and participating in test plan reviews;
• Developing scalable verification components;
• Random-constrained stimulus;
• Debugging regression failures;
• Post-Silicon debug and Feedback Integration into design or verification Flow; and
• Code coverage closure.

Can work remotely.

Preferred Skills: N/A

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.