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EdgeCortix

Fabless AI accelerator designer for edge

Senior Electronic Engineer

Board & Electronics DesignConfirmed live in the last 24 hours
Full-timeVirginia, USANo salary listed

About the Job

Requirements

  • A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.
  • At least 5 years of proven experience designing complex, high-density, multilayer (12+ layers) PCBs implementing high-speed protocols such as 25G/56G/112G Ethernet, DDR4/DDR5, or PCIe Gen 3+.
  • High proficiency with major schematic-capture and PCB-layout tools such as Cadence OrCAD/Allegro or Altium Designer.
  • Hands-on experience, directly or indirectly, with signal-integrity and power-integrity simulation software such as Ansys HFSS/SIwave or Cadence Sigrity.
  • Strong debugging and troubleshooting skills, and proficiency with high-speed digital test equipment.
  • Deep understanding of high-speed data transmission and power-electronics design, including multiphase buck converters and PMICs for high-power accelerators.
  • Experience with and appreciation of PCB fabrication, SMT assembly, and PCBA thermal management.

Responsibilities

  • Lead design and development of next-generation, high-speed PCIe-based hardware products throughout the hardware development lifecycle, from architecture and high-speed schematic design through multilayer PCB-layout supervision, signal-integrity analysis, lab bring-up, and production transition.
  • Specify requirements, select components, capture schematics, and manage bills of materials.
  • Lead the design and schematic capture of complex multilayer digital boards featuring power-delivery networks, high-speed SerDes and PCIe Gen 4/5/6 interfaces, BMCs, AI accelerators, FPGAs, CPUs, and high-speed memory such as LPDDR5x.
  • Analyze and optimize data transmission characteristics such as eye diagrams, crosstalk, and jitter, and power-delivery networks for accuracy, noise, voltage drop, and thermal performance, using simulation tools independently or in collaboration with simulation engineers.
  • Guide PCB-layout designers and thermal-mechanical engineers on material and stack-up selection, high-speed routing and power-delivery constraints, component placement, and thermal-management strategies.
  • Define and lead hands-on board bring-up, debugging, characterization, and validation in the lab.
  • Partner with firmware and driver teams to ensure proper operation of AI-acceleration workloads and integration into deployable systems.
  • Design for and support regulatory-compliance testing, including EMI/EMC, safety, protocol compliance, interoperability, and environmental-reliability validation.
  • Create and assemble reference-design guides, schematic documentation, layout notes, block diagrams, operational concepts, and validation procedures to help external customers recreate and modify products for chip-down designs of AI-accelerator chips.
  • Support the Marketing team in preparing polished, customer-ready documentation and solutions that facilitate customer adoption and accelerate design-in activities.

Desired Qualifications

  • Direct experience with PCIe board development, with Gen 3 or Gen 4 as a minimum; Gen 5 or Gen 6 experience is a plus.
  • East Coast time-zone location; Washington, DC/DMV-area candidates are a plus.

About the Company

EdgeCortix

Fabless AI accelerator designer for edge

EdgeCortix designs energy-efficient AI accelerators and software for edge computing in a fabless model, co-designing hardware and software to optimize AI performance on edge devices. Its main products are AI-specific processors and a software platform that, together, enable deploying AI at the edge with low power consumption. Unlike typical hardware vendors, EdgeCortix emphasizes software-centric co-design to maximize efficiency, aiming to deliver scalable edge intelligence for sectors like defense, robotics, and automotive. The company’s goal is to enable practical, power-conscious AI processing on edge devices, supporting broad deployment through its integrated hardware-software ecosystem and ongoing growth funded by investors.

Company size
51-200
Company stage
Debt Financing
Total funding
$197M
Headquarters
Tokyo, Japan
Founded
2019

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