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FuriosaAI

Power-efficient AI inference accelerator chips

Scale-Up Ethernet Engineer

Hardware Systems IntegrationUpdated on Nov 10
Full-timeNo salary listed

About the Job

Requirements

  • Understand the operation of data-center Ethernet networks, including switches, lossless networking, and RDMA, and have experience configuring and debugging network devices or systems in Linux.
  • Have experience developing or debugging semiconductor system software at the register or memory-map level, such as SoC firmware, device drivers, or silicon bring-up and diagnostic software.
  • Have practical experience with bring-up, integration validation, or performance analysis for rack- or cluster-scale systems combining servers, switches, and accelerators.
  • Be able to automate test execution, device control, and log collection using Python or shell scripts.
  • Actively use AI tools, including large language models and coding agents, in work and verify their outputs using evidence.
  • Be able to form hypotheses based on packets, logs, and performance counters and narrow down root causes through reproducible experiments.
  • Be able to collaborate with engineers across specialties and clearly document validation methods and results.

Responsibilities

  • Validate Scale-Up Ethernet endpoint controller IP integrated into accelerator SoCs, from pre-silicon prototypes through silicon, and work with RTL and firmware engineers to resolve issues involving on-chip buses, DMA, memory maps, interrupts, and firmware.
  • Configure NICs and switches for traffic characteristics, validate switch network operating system behavior and Scale-Up link-layer operations such as buffers, queues, PFC, LLR, and CBFC, improve performance and stability under congestion, and evaluate current Scale-Up switches.
  • Reproduce data-transfer errors and performance bottlenecks using packet captures, device counters, logs, and telemetry, and isolate whether root causes lie in hardware, firmware, drivers, software, or the fabric.
  • Build clusters that generate collective communication such as all-reduce and all-to-all, as well as LLM inference and training traffic; identify issues and corner cases, measure bandwidth, latency including tail latency, and stability, and validate configuration changes and performance regressions.
  • Analyze MAC, PCS, FEC, and SerDes status and error counters; validate link stability and interoperability across optical modules, DAC, AEC, and AOC cables, and switch-port combinations; use CMIS to check module application modes, firmware versions, temperature, and optical power; and test link stability across repeated resets and temperature changes.
  • Design and build rack and fabric management systems that bring node BMCs, switches, power shelves, BBUs, PDUs, and cooling devices under a rack manager; manage inventory, power sequencing, remote control, and firmware updates; use Redfish and PLDM for nodes and gNMI/YANG for switches; define APIs for an upstream orchestrator with reference to OpenRMC and OCP specifications; and design Scale-Up fabric management functions including endpoint identity and address assignment, topology discovery, link bring-up sequence, and domain partitioning.
  • Build rack-level observability for power, temperature, links including lane-level FEC, optical modules, and device status; design fault detection, isolation, fail-safe recovery, and reliability, availability, and serviceability scenarios; and validate them through fault injection.
  • Configure and validate Scale-Up Ethernet rack systems comprising compute trays with NPUs and NICs, switch trays, power shelves, management networks, and DAC, AEC, AOC, and optical cabling; perform staged validation from link bring-up through rack integration; and lead a proof of concept to migrate the current rack validation environment to an Open Rack or other OCP-standard configuration.
  • Automate remote console and PDU control, test execution, and result collection, and build dashboards and technical documentation for long-duration stability testing and regression validation.
  • Orchestrate work using AI agents such as Claude Code and Codex for equipment bring-up, builds, test execution, log analysis, and documentation; design equipment reservation and locking, remote-control APIs, and job queues so agents can share lab equipment without conflicts; and verify agent results against evidence.
  • Incorporate OCP standards including ESUN, Open Rack, and Hardware Management, UEC, and SONiC Scale-Up Working Group developments into designs, and collaborate with switch, power, BMC, and validation-equipment vendors.

Desired Qualifications

  • Experience with link bring-up, performance evaluation, or interoperability validation in 100G–800G Ethernet environments.
  • Understanding or practical experience with MAC, PCS, FEC, SerDes, QSFP-DD and OSFP optical modules, DAC, AEC, and AOC cables, and CMIS-based module management.
  • Experience designing rack-scale copper and optical cabling, or qualifying cables and modules through interoperability testing across vendors and production lots.
  • Experience configuring lossless Ethernet fabrics and tuning congestion control, including PFC, ECN, buffers, and queues.
  • Understanding of switch network operating system architecture and behavior, and experience with Broadcom Tomahawk switches.
  • Experience analyzing performance bottlenecks involving DMA, remote memory access, and collective communication such as all-reduce and all-to-all in NPU or GPU accelerator systems.
  • Experience validating operation between Ethernet controller IP and SoCs, including on-chip buses, DMA, and memory subsystems, or tracing issues with driver, firmware, and hardware teams at the C/C++ or RTL level.
  • Experience with rack or server management using BMC/OpenBMC, Redfish, PLDM/MCTP, or OpenRMC, including inventory, firmware updates, power and thermal control, and fault recovery, or developing and operating rack-manager or fleet-management systems.
  • Experience building hardware test labs, CI-based regression validation, telemetry, or long-duration stability-testing infrastructure.
  • Experience creating and operating workflows that delegate work to multiple AI agents, including equipment-control APIs, session and job management, and result-validation harnesses.
  • Experience with OCP rack hardware such as Open Rack (ORv3/ORW), 48 V or 800 VDC power, power shelves, or BBUs, or bringing up racks with an ODM.
  • Understanding of Scale-Up standards such as OCP ESUN/SUE-T, UEC (LLR, CBFC), and UALink, or participation in OCP or SONiC communities.

About the Company

FuriosaAI

Power-efficient AI inference accelerator chips

FuriosaAI develops AI accelerators for data centers. Its flagship RNGD chip is a power-efficient accelerator designed to boost performance per watt for running large language models and other demanding AI workloads. The hardware is configurable with multiple processing elements to fit different workloads, and it is paired with advanced compiler technology and profiling tools to identify bottlenecks and optimize efficiency. This combination of flexible hardware and software optimization differentiates FuriosaAI from competitors, focusing on maximizing performance while keeping energy use low. The company targets data centers and enterprises that need high-performance, energy-efficient AI solutions, and aims to make AI computing more sustainable and scalable by selling its chips and related software tools and pursuing long-term contracts with large-scale customers.

Company size
201-500
Company stage
Series D
Total funding
$887.5M
Headquarters
Seoul, South Korea
Founded
2017

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