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Renesas Electronics

Automotive-focused MCUs, SoCs, analog devices

Staff Digital Engineer

Full-Time
No salary listed
Senior, Expert
Bachelor's
Chandler, AZ, USA
In PersonWillingness to travel domestically or internationally on short notice is required.

About the job

Requirements
  • >10 years of digital design experience in wireless handheld, data conversion, or power management applications.
  • A degree-level qualification in Electrical Engineering, Electronics, Computer Engineering, Computer Science, or a related discipline.
  • Fluency in Verilog and SystemVerilog RTL for digital CMOS circuit design.
  • Strong understanding of ASIC design methodology.
  • Strong understanding of Lint, CDC, and RDC tools.
  • Strong understanding of block-level and chip-level verification techniques.
  • Proven ability to debug RTL and gate-level simulations.
  • Mandatory competence in written and verbal English.
  • Willingness to travel domestically or internationally on short notice.
  • Ability to work independently and collaboratively.
Responsibilities
  • Interpret high-level requirements to architect, design, and integrate low-power digital circuits for mixed-signal data conversion and power management products in advanced process nodes.
  • Support the full product lifecycle from concept to mass production and communicate with the wider organization throughout silicon development.
  • Provide technical leadership and influence to the digital design team through technical discussions and reviews, mentor junior engineers, and support recruitment.
  • Work closely with analog and verification engineers to deliver high-quality silicon solutions.
  • Ensure the digital development process is state-of-the-art and achieves budget, schedule, and project deliverable goals.
  • Design digital RTL that meets timing, area, power, and applicable standards specifications.
  • Integrate designs at the top level and run block-level and top-level simulations.
  • Participate in mixed-signal design flow activities, including micro-architecture, design partitioning, RTL Verilog/SystemVerilog design, timing-constraint generation, synthesis, interaction with the place-and-route team, timing analysis, Lint, CDC, RDC, and UPF.
  • Work with the place-and-route team to generate a layout meeting timing, area, and power requirements.
  • Support DFT strategy and implementation and review test-case development.
  • Assist with top-level testbench debugging and run RTL and gate-level simulations.
  • Work with analog and digital verification engineers to develop complex test scenarios for pre-silicon verification.
  • Support the analog team in developing AMS, SystemVerilog, or Verilog-real behavioral models.
  • Develop detailed block-level and chip-level design documents and collateral.
  • Hold and participate in key design reviews and complete associated checklists.
  • Perform silicon evaluation as required.
  • Document device errata, develop workaround solutions, and implement engineering changes when necessary.
Desired Qualifications
  • Experience with Digital Signal Processing concepts and hardware realizations.
  • Experience with methodology and flow automation using appropriate scripting.
  • Experience with mixed-signal design methodologies.
  • Experience developing design constraints and handing designs off to the place-and-route team.
  • Experience with static timing analysis and timing closure.
  • Experience with low-power design techniques, including clock gating, power gating, and UPF.
  • Experience with power analysis and optimization.
  • Experience with advanced verification methodologies such as UVM.
  • Experience with industry-standard protocols such as AMBA or I2C.

About the company

Renesas Electronics designs and manufactures semiconductor components, including microcontrollers, system-on-a-chip solutions, and analog and power devices for automotive, industrial, infrastructure, and IoT markets. Its chips serve as building blocks inside customers’ electronic products, and it offers Winning Combinations—pre-tested system architectures that combine Renesas parts with technologies from its acquisitions to speed development. The company differentiates itself through a broad, integrated portfolio built via acquisitions and a planned unified digital design platform that streamlines integration with hardware and software. Its goal is to be a leading supplier of MCUs, SoCs, and analog/power devices while providing a single, connected design ecosystem that shortens customers’ development cycles.

Company Size

10,001+

Company Stage

IPO

Headquarters

Tokyo, Japan

Founded

2002

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Simplify's Take

What believers are saying

  • Renesas launched 650V dual-side-cooled GaN on September 30, 2026 for megawatt AI data centers.
  • Renesas completed Altium on May 29, 2026 and Pictorus on June 18, 2026.
  • TIER IV collaboration on August 20, 2026 expands Renesas into open autonomous-driving platforms.

What critics are saying

  • Renesas sued Navitas on July 22, 2026, and Navitas countersued August 10, 2026.
  • Takasaki factory production ends within two to three years, signaling legacy manufacturing strain.
  • GaN and autonomous-driving bets face execution risk if AI-data-center and SDV wins slip.

What makes Renesas Electronics unique

  • Altium plus Pictorus unify Renesas 365, spanning design, simulation, and deployment.
  • R-Car Gen 5 anchors open Autoware partnerships across Level 2+ to Level 4 autonomy.
  • Renesas leads automotive MCU, analog, and power silicon for high-reliability embedded systems.

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Benefits

Health Insurance

Life Insurance

Mental Health Support

Professional Development Budget

Meal Benefits

Growth & Insights and Company News

Headcount

6 month growth

↓ -21%

1 year growth

↓ -30%

2 year growth

↓ -30%
Yahoo Finance
Sep 30th, 2026
Renesas launches industry's first 650V GaN chip with dual-side cooling for megawatt-scale AI data centres

Renesas Electronics has launched the industry's first 650V gallium nitride device with dual-side cooling for AI data centres. The TP65H020G4PLSGBD delivers 20 milliohms on-resistance in an 8x8mm package, 57% smaller than existing alternatives. The device targets 800V DC/DC intermediate bus converters in megawatt-scale data centres, addressing space and thermal constraints as rack power approaches megawatt levels. Dual-side cooling reduces top-side thermal impedance by 10% whilst maintaining compatibility with standard silicon gate drivers. Renesas is currently sampling the device to major data centre manufacturers. A 6kW reference design achieved 2.6 kW/in³ power density with 0.21% higher efficiency than equivalent alternatives. Mass production is planned for mid-2027. The device will be showcased at OCP Global Summit in San Jose, California, from 12-15 October.

PR Newswire
Sep 1st, 2026
Autoware Foundation partners with Renesas to deliver open-source end-to-end AI for ADAS and autonomous driving

The Autoware Foundation has partnered with Renesas Electronics to deliver open-source AI software for advanced driver assistance systems and autonomous driving. Renesas has joined the foundation at its highest membership tier. The collaboration integrates Autoware's end-to-end AI stack with Renesas R-Car system-on-chip platforms. This enables automotive manufacturers and Tier-1 suppliers to develop scalable solutions ranging from entry-level L2 driver assistance to L2++ hands-free autopilot and L4 robotaxis. The partnership allows OEMs to customise the Apache 2.0-licensed software for specific vehicles and use cases, offering a flexible alternative to in-house development or commercial solutions. The companies describe this as a watershed moment for the industry, comparing it to Linux's impact on computing. "This is the Linux moment for the ADAS and autonomous driving industry," said Christian John, board director at the Autoware Foundation.

Business Wire
Aug 27th, 2026
Renesas opens Physical AI & Robotics Lab in Beijing to advance humanoid robot development

Renesas Electronics has opened a Physical AI & Robotics Lab in Beijing to help customers develop and validate next-generation robotic systems. The facility will support the company's physical AI strategy, focusing on systems that perceive, decide and act in real time in physical environments. Physical AI represents AI's evolution beyond digital applications into robotics and other real-world systems. The lab will integrate hardware, software, AI modelling, control, power supply and sensing to support complete solution development. Renesas currently addresses roughly 30% of the humanoid robot bill of materials and aims to expand that to 70%. The company established a Physical AI Division on 1 July 2026 to focus on this growth area. The Beijing lab will serve as a platform connecting customers, ecosystem partners, universities and startups to accelerate robotics innovation in China's thriving robotics market.

Renesas Electronics Corporation
Aug 25th, 2026
Renesas Completes Acquisition of Integrated Device Technology

TOKYO, Japan, March 30, 2019 JST | San Jose, California, U.S.A., March 29, 2019 PST― Renesas Electronics Corporation (TSE: 6723, “Renesas”), a premier supplier of advanced semiconductor solutions, and Integrated Device Technology, Inc. (“IDT”), a leading supplier of analog mixed-signal products, including sensors, connectivity and wireless power, today jointly announced the successful completion of Renesas’ acquisition of IDT, as of March 30, 2019 JST, March 29, 2019 PDT, following approvals by IDT shareholders and the relevant regulatory authorities.

PR Newswire
Aug 20th, 2026
TIER IV partners with Renesas to build open AI computing platform for autonomous vehicles

TIER IV is collaborating with Renesas Electronics to build an open AI-native computing platform for software-defined vehicles. The partnership combines TIER IV's Autoware autonomous driving software and reference AI models with Renesas' R-Car Gen 5 automotive system-on-chips. The collaboration aims to deliver scalable solutions spanning Level 2+ advanced driver assistance through Level 4 autonomous driving. TIER IV will port and optimise Autoware on R-Car Gen 5 SoCs and deploy its end-to-end autonomous driving AI models on the platform. The companies will jointly promote this integrated hardware and software platform to automakers and Tier 1 suppliers worldwide. TIER IV plans to demonstrate Autoware and its reference AI models running on Renesas' R-Car X5H at Automotive World 2026 in September at Makuhari Messe near Tokyo.