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Keysight introduces PCIe 7.0 Protocol Test Solution to accelerate AI infrastructure validation. Instant link-up and deep protocol visibility reduce risk and shorten next generation system development Keysight Technologies, Inc. (NYSE: KEYS) today introduced its Protocol Test Solution for PCIe(R) 7.0, an integrated platform that enables engineers to bring up, validate, debug, and verify compliance of next-generation devices and systems at the protocol layer. By combining instant link-up with deep visibility at 128 GT/s, the solution helps development teams identify issues earlier, reduce validation risk, and accelerate the delivery ofnext generationhigh-speed PCIe interconnect required for artificial intelligence and data center infrastructure. As artificial intelligence workloads increase demand for computeand databandwidth, PCI Express(R) 7.0 provides next generation interconnect performance by doubling the raw data rate to 128 GT/s. PCI Express 7.0 is expected to become the dominate interconnect for rack-scale systems connecting graphics processing units, accelerators, switches, memory, and storage. This performance increase makes link establishment, protocol behavior, and interoperabilitymore difficult to validate across increasingly complex architectures. Reliable link-up is the foundation for meaningful protocol analysis. At the fastest PCIe speeds, engineers need immediate visibility to investigate link training and status state machine (LTSSM) behavior, FLIT-based encoding, protocol errors, and complex transaction layer issues to isolate problems before they lead to redesigns or cause schedule delays. Keysight addresses this challenge with an architecture designed to provide stable and reliable analysis without analyzer tuning, helping teams move from connection to actionable insight faster. The solution combines a full-featured protocol analyzer and exerciser, test platform, and dedicated analysis software. The integrated workflow offers early adopters both a link partner for device bring-up and extensiveprotocol visibility needed to progress from initial silicon validation through interoperability and compliance testing. Key benefits of the Protocol Test Solution for PCIe 7.0 include: * Accelerates time to first measurement: Advanced signal integrity enables reliable protocol trace capture without analyzer tuning, giving engineers repeatable results and faster insight. * Identifies protocol issues faster: Deep visibility intoLTSSM transitions, FLIT-based encoding, protocol errors, and transaction layer packet transactionshelp teams accelerate debug, isolate root causes, validate reliable operation, and verify compliance to PCI Express specifications. * Reduces early silicon risk: Early collaboration and test availabilityhelp teams uncover protocol and interoperability issues sooner, minimizing late-stage rework and shortening development cycles. * Streamlines end-to-end validation: An integrated analyzer, exerciser, test platform, and software environment provides a consistent workflow from bring-up through validation and compliance testing. * Advances AI infrastructure development: Support for rack-level interconnects and backward compatibility helps engineers validate next-generation scale-up architectures while protecting existing test investments and easing migration. Neeraj Paliwal, Senior Vice President, Silicon IP Product Management, Synopsys, said: "Establishing a reliable PCIe 7.0 link at 128 GT/s between production silicon and protocol test equipment is a key interoperability milestone. Validating our silicon-proven Synopsys PCIe 7.0 IP solution with Keysight's protocol solution means customers can commit to their next-generation AI and data center designs with confidence." Dr. Joachim Peerlings, Vice President of Network and Data Center Solutions, Keysight, said:"Successful PCIe 7.0 deployment depends on proven ecosystem interoperability alongsidebandwidth advancements. Our collaboration with Synopsys helps customers validate designs earlier, identify issues faster, and gain confidence in the readiness of next-generation silicon and systems. Together, we're accelerating the path from innovation to deployment for AI and data center applications." Keysight will demonstrate the Protocol Test Solution for PCIe 7.0 at OCP Global Summit 2026, October 13-16, 2026, in San Jose, California.

Keysight Technologies (NYSE: KEYS) has launched FITS-16CH, a system that validates digital-layer error performance in optical and copper interconnects. It has 16 transmit and 16 receive channels, twice the density of the FITS-8CH. The platform combines bit error ratio and forward error correction measurements to show how complete interconnect assemblies perform in real-world conditions. It supports 106G and 212G lane rates for 800G interconnects and emerging 1.6T technologies. An automated tuning tool can cut transmit tuning from hours, days, or weeks to a few minutes. The system works with Keysight analyzers, bit error ratio testers, and oscilloscopes. Credo Technologies' Ameet Suri said the tool lets the company test active electrical cables at system level during development and qualification.

Simplifying device testing from DC to 250GHz. Wednesday 14th October 2026 Keysight, Glasgow University, NPL and MPI develop single-sweep method for continuous on-wafer InP HEMT characterisation Keysight Technologies has collaborated with the University of Glasgow, the National Physical Laboratory (NPL), and MPI to develop a new approach to broadband characterisation of next-generation sub-terahertz (sub-THz) semiconductor devices. Together, the organisations demonstrated continuous on-wafer characterisation of InP HEMTs from near DC to 250 GHz in a single sweep, simplifying broadband measurements for advanced semiconductor research and design. As semiconductor technologies move into mmWave and sub-terahertz frequencies for next-generation applications, engineers need to accurately characterise transistor performance across increasingly broad frequency ranges. Conventional approaches can require multiple measurement setups and calibrations, adding complexity and making it more difficult to obtain consistent data for broadband device modeling. The four organisations combined Keysight instrumentation, University of Glasgow semiconductor devices, MPI Corporation on-wafer probing technology, and NPL metrology expertise to create the broadband measurement solution. The Keysight tools included the PNA-X Vector network analyser; the Single-Sweep 250 GHz frequency extender; and its Precision Source/Measure Unit (SMU). Together, these technologies enabled continuous measurement from near DC to 250 GHz with a single probe touchdown, eliminating the need for multiple setup changes and providing consistent broadband S-parameter measurements. Built-in source filtering and broadband source power calibration also helped ensure signal purity of the applied mmWave signal at the probe-tip. Thierry Locquette, VP of sales, Europe, Middle East & Africa at Keysight said: "Characterising devices continuously from near DC to 250 GHz in a single sweep can significantly simplify the measurement process for researchers developing next-generation semiconductor technologies. By bringing together expertise in instrumentation, devices, probing, and metrology, this collaboration demonstrates a practical approach to generating the consistent broadband data engineers need to accelerate device development." Xiaobang Shang, principal scientist and On-wafer Measurement Lead at NPL, said: "Accurate on-wafer measurement is essential for developing reliable semiconductor devices, particularly as technologies move further into the millimetre-wave and sub-terahertz frequency ranges. We were pleased to contribute NPL's high-frequency on-wafer metrology and calibration expertise to this collaboration, helping demonstrate a practical route to consistent broadband device measurements using the state-of-the-art single sweep system." Matthew White, director of Business Development at MPI, said: "Extending on-wafer characterisation to 250 GHz requires the probing, calibration, and measurement platform operating as one seamlessly integrated system. This collaboration demonstrates a practical approach to achieving consistent broadband measurements from near DC to 250 GHz with a single probe touchdown, helping researchers simplify characterisation and accelerate device development with great confidence." SPONSOR MESSAGE Unifying software and semiconductor development. Software-defined workflows are reshaping the way smart, connected products are designed. The merging of software functionality and hardware intricacies is pushing traditional workflows beyond their capabilities, leaving teams at a developmental crossroads. With this fundamental shift comes the critical need for end-to-end traceability and robust collaboration tools that easily integrate into existing workflows to unify hardware and software development. In this new software-defined era, how can companies break down the silos that have historically defined software and silicon development workflows?