Design For Test Senior Lead Engineer

At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.

Key Responsibilities
Conduct DFT Engineering Tasks: DFT Audit/Scan Logic/MBIST Logic/BSCAN Logic Insertion.
- Responsible for implementing the Hardware DFT features that support ATE, in-system test, debug and diagnostics needs of the design
- Responsible for development of innovative DFT IP in collaboration with the cross-functional teams, and play a key role in full chip design integration with the testability features integrated in the RTL
- Work closely with the design/design-verification and physical design teams to enable the integration and validation of the Test logic in all phases of the design, and back-end implementation flow
- Analyze timing report and suggest for the solution
- Skillful in gate-level simulations with and without timing annotations
- Diagnose and analyze data logs during silicon bring-up phase to finalize prototype patterns
- Be responsible for Innovative Hardware DFT for new silicon device models, bare die & stacked die-driving re-usable test and debug strategies

We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard.

We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.

– 4+ years of DFT engineering experience

– Strong understanding of scan and compression (EDT) design at top and block level

– Familiar with OCC architecture for both stuck-at/transition modes
– Good knowledge of MBIST, BIRA, and BISR
– Strong experience in analyzing ATPG fault lists to get high test coverage
– Experience in gate-level simulations with and without timing annotations 
– Knowledge of Verilog HDL and experience with simulators and waveform debugging tools
– Understanding of Design verification (DV) methodologies for validating DFT implementation in simulation pre-silicon
- Familiar with programming language: Shell, Perl, Tcl
- Experience in EDA DFT tools
- Good scripting skills and the ability to design and debug with minimal oversight