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Synopsys

EDA software for chip design

ASIC Digital Design Senior Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timePorto, PortugalNo salary listedIn-person

About the Job

Requirements

  • A Master of Science or PhD in Electrical Engineering or Computer Science is required.
  • At least 3 years of strong working knowledge of RTL design for hardware IP components, including hands-on experience writing synthesizable SystemVerilog.
  • Ability to create detailed specifications for test environments.
  • Proficiency in ASIC verification using SystemVerilog, Universal Verification Methodology, and/or Verilog.
  • Strong understanding of integrated circuit design flows and problem-solving and debugging skills.
  • Strong written and verbal communication skills.
  • Ability to collaborate in an international team environment.
  • Innovative thinking and passion for technology and continuous improvement.
  • Attention to detail and commitment to delivering high-quality work.
  • Adaptability and ability to manage multiple tasks effectively.

Responsibilities

  • Design and implement RTL in Verilog and SystemVerilog for Security IP cores, translating security requirements into synthesizable, verifiable hardware.
  • Build and maintain test environments for digital hardware Security IP using SystemVerilog and Universal Verification Methodology, ensuring coverage of corner cases and attack scenarios.
  • Verify IP cores and subsystems using modern verification techniques, including Universal Verification Methodology testbenches and formal verification tools.
  • Collaborate with hardware and software security engineers to analyze functional correctness and performance of embedded IP solutions across threat models.
  • Contribute to detailed design specifications, verification plans, and documentation that support global development and customer integration.
  • Work within an international team across time zones, coordinating design reviews, debugging sessions, and milestone deliveries.

Desired Qualifications

  • Experience with hardware security concepts or cryptographic IP.

About the Company

Synopsys

EDA software for chip design

Synopsys provides software tools and services for electronic design automation (EDA), helping engineers design, simulate, verify, and optimize semiconductor chips and systems. Its products cover the full design flow, including RTL-to-gating synthesis, place-and-route, timing analysis, verification, and silicon validation, as well as software integrity solutions and hardware-assisted verification. Engineers use these tools to model, simulate, and validate complex chip designs before manufacturing, reducing bugs and improving performance. Compared with many competitors, Synopsys differentiates itself through its broad, end-to-end design toolchain, large ecosystem of IP and integration with simulation and modeling capabilities gained from its 2025 merger with ANSYS, and its global scale and support. The company aims to help designers push the boundaries of chip and system performance, accelerate time-to-market, and enable silicon-to-systems design across a wide range of industries.

Company size
10,001+
Company stage
IPO
Headquarters
Sunnyvale, CA
Founded
1986

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