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Synopsys

EDA software for chip design

ASIC Digital Verification Design – Principal Engineer

Hardware Validation & TestingConfirmed live in the last 24 hours
Full-timeUnited StatesIn-person

About the Job

Requirements

  • A Bachelor of Science in Electrical Engineering (BSEE) and at least 8 to 10+ years of direct industry experience verifying complex ASIC or SoC designs.
  • Deep expertise with SystemVerilog and Universal Verification Methodology (UVM).
  • Strong protocol knowledge in one or more of PCI Express (PCIe), Compute Express Link (CXL), DDR memory interfaces, or Ethernet.
  • Experience developing constrained-random and coverage-driven verification environments.
  • Strong debugging and problem-solving skills spanning RTL, verification, and protocol compliance.
  • Experience with industry-standard simulators such as VCS, ModelSim, or similar tools.
  • Ability to independently drive technical initiatives while collaborating across geographically distributed teams.

Responsibilities

  • Own verification of complex Interface IP solutions, including PCIe, CXL, DDR, and Ethernet technologies.
  • Architect, develop, and enhance scalable UVM-based verification environments and reusable verification IP.
  • Define verification strategies and test plans from specification review through product release.
  • Develop constrained-random, coverage-driven verification solutions using SystemVerilog and UVM.
  • Drive functional coverage closure and verification signoff activities.
  • Debug challenging RTL, protocol, and system-level issues while improving verification efficiency and automation.
  • Partner with architecture, RTL, firmware, and systems teams to identify issues early and ensure robust product quality; mentor engineers contributing to verification methodology improvements across the organization.
  • Deliver robust, high-quality verification solutions for complex Interface IP products.
  • Improve verification coverage, reusability, and execution efficiency.
  • Influence verification methodologies and best practices across engineering teams.
  • Drive successful product releases with exceptional quality standards.
  • Help develop the next generation of verification talent through technical mentorship and leadership.

Desired Qualifications

  • Experience with verification IP development, assertion-based verification, and formal methodologies, with knowledge of modern SoC architectures and high-speed communication interfaces.

About the Company

Synopsys

EDA software for chip design

Synopsys provides software tools and services for electronic design automation (EDA), helping engineers design, simulate, verify, and optimize semiconductor chips and systems. Its products cover the full design flow, including RTL-to-gating synthesis, place-and-route, timing analysis, verification, and silicon validation, as well as software integrity solutions and hardware-assisted verification. Engineers use these tools to model, simulate, and validate complex chip designs before manufacturing, reducing bugs and improving performance. Compared with many competitors, Synopsys differentiates itself through its broad, end-to-end design toolchain, large ecosystem of IP and integration with simulation and modeling capabilities gained from its 2025 merger with ANSYS, and its global scale and support. The company aims to help designers push the boundaries of chip and system performance, accelerate time-to-market, and enable silicon-to-systems design across a wide range of industries.

Company size
10,001+
Company stage
IPO
Headquarters
Sunnyvale, CA
Founded
1986

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