ITRI

EDA Design Intern

Silicon & ASIC DesignConfirmed live in the last 24 hours

InternshipZhudong Township, TaiwanNo salary listed

A Master's or Ph.D. degree is required.
Educational or research background relevant to AI-driven electronic design automation, chip layout optimization, numerical analysis, or system-on-chip/intellectual property verification is required or desired.
Must be able to work on-site at the Hsinchu Zhongxing Campus.

Develop fully automated parameter exploration and optimization algorithms and tools based on existing electronic design automation platforms.
Design and implement 2.5D/3D chip layout algorithms with considerations for power, performance, and area.
Develop next-generation numerical analysis and computational solvers to accelerate convergence speed.
Develop generative programming-based intellectual property and system-on-chip verification technologies to improve verification efficiency and convergence.

This internship is in ITRI's Electronics and Optoelectronics Systems Research Laboratories (EOSL).

Intern will work on the following topics / tasks:

AI-Driven EDA Development and Research

Develop fully automated parameter exploration and optimization algorithms and tools based on existing EDA platforms.
Design and implement 2.5D/3D chip layout algorithms with considerations for power, performance, and area (PPA).
Develop next-generation numerical analysis and computational solvers to accelerate convergence speed.
Develop generative programming–based IP and SoC verification technologies to improve verification efficiency and convergence.

Qualifications:

Major and student level: Master's or Ph.D. degree.
Required/desired background with specific skills (software, equipment, processes, etc.): Educational or research background relevant to AI-driven EDA, chip layout optimization, numerical analysis, or SoC/IP verification.
Language or other qualifications: Must be able to work on-site at the Hsinchu Zhongxing Campus.

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