Staff Design Verification Engineer - Cache Verification

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. 

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Job Description:

The Role

SiFive is looking for a Staff Design Verification Engineer to drive verification of cache and memory-subsystem functionality, with an emphasis on cache coherency, ordering, correctness, and subsystem integration.

This is a Staff Engineer individual-contributor role within the horizontal cache verification area. We are looking for someone who can independently execute high-quality verification work, build robust environments, debug complex issues efficiently, and contribute to stronger verification methodology across the team.

Responsibilities

• Own verification planning and execution for L2/L3 cache and related cache-subsystem features, from block-level verification through subsystem integration.
• Develop and maintain verification environments, checkers, scoreboards, assertions, stimulus, and coverage models for cache coherency, ordering, flow control, and error scenarios.
• Define and execute directed and constrained-random tests that expose corner cases in coherency, concurrency, backpressure, and integration behavior.
• Analyze failures, isolate root cause, and drive fixes across RTL, testbench infrastructure, assertions, and test content.
• Collaborate closely with architecture, design, and verification teams to clarify requirements, review specifications, and improve verification quality early in the development cycle.
• Write functional coverage, analyze coverage results, and close coverage holes to ensure verification completeness and signoff quality.
• Contribute reusable methodology, automation, and debug improvements that raise team-wide productivity and verification quality.

Minimum Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 7+ years of experience in ASIC, CPU, or SoC design verification, with strong hands-on ownership of complex verification problems at block or subsystem level.
• Strong expertise in SystemVerilog and UVM-based verification.
• Strong understanding of cache architecture, memory hierarchy, and cache coherency protocols/behavior.
• Experience building reusable testbenches, assertions, checkers, scoreboards, coverage models, and debug infrastructure.
• Strong debugging skills with the ability to root-cause issues across specification, RTL, and testbench layers.
• Experience with coverage analysis and closure, constrained-random verification, and metrics-driven signoff.
• Strong understanding of computer architecture and microarchitecture fundamentals.

Preferred Qualifications

• Direct experience verifying multiple levels of cache, including private and shared cache structures.
• Experience with cache coherency, memory consistency, weak ordering, and multicore verification challenges.
• Experience with performance-oriented verification, formal techniques, or emulation/FPGA-assisted debug.
• Familiarity with Python, C/C++, or scripting languages used for DV infrastructure and automation.
• Ability to influence technical direction across architecture, design, and verification teams.

What Success Looks Like

• Verification plans are complete, concrete, and aligned to real architectural risk areas.
• Critical cache and coherency bugs are found early, reproduced efficiently, and closed with durable fixes.
• Coverage and verification quality improve meaningfully under your ownership.
• The cache verification effort becomes more scalable, predictable, and reusable because of your contributions.
• Architecture and design teams rely on you as a strong technical partner for difficult verification and debug problems.

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

Taiwan

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.