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MemryX

Edge AI processing accelerator chips

Senior Director of Hardware Engineering

Engineering LeadershipConfirmed live in the last 24 hours
Full-timeAnn Arbor, MI, USAIn-person

About the Job

Requirements

  • A master's degree or higher in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • 15+ years of experience developing complex ASICs, SoCs, processors, accelerators, or related semiconductor products.
  • Technical leadership experience, including leading ASIC/SoC engineering teams and complex chip development programs.
  • Multiple successful ASIC/SoC tapeouts with direct involvement across major stages of the chip development lifecycle.
  • Deep understanding of digital IC design, including architecture, microarchitecture, RTL design, verification, synthesis, timing, physical design, design for test, and silicon bring-up.
  • Strong understanding of SoC architecture, memory systems, high-speed interfaces, clock/reset architecture, power management, and chip-level integration.
  • Experience making performance, power, area, cost, and schedule tradeoffs for production silicon.
  • Ability to review technical designs in depth and work directly with engineers to resolve difficult architecture and implementation problems.
  • Experience working with IP vendors and external design service companies.
  • Experience planning and executing ASIC programs across internal teams and external partners.
  • Ability to work effectively with architecture, software, product, operations, and executive teams.
  • Ability to lead in a fast-moving environment where requirements evolve and engineers must balance technical ambition with execution risk.

Responsibilities

  • Lead and grow the hardware engineering team responsible for the design and implementation of MemryX AI accelerator chips.
  • Drive chip development from product requirements and architecture through RTL design, verification, physical implementation, tapeout, silicon bring-up, and production.
  • Work with cross-functional teams to define next-generation AI accelerator architecture, SoC architecture, memory hierarchy, interfaces, performance targets, and product requirements.
  • Translate system- and product-level requirements into hardware architecture and implementation specifications.
  • Lead technical tradeoff analyses across performance, power, area, cost, schedule, and implementation risk.
  • Provide hands-on technical leadership and design reviews across compute architecture, memory subsystem, SoC integration, interconnect, and external interfaces.
  • Establish development plans, milestones, ownership, and execution processes for complex ASIC programs.
  • Identify technical and schedule risks early and drive engineering teams toward practical solutions.
  • Coordinate with software, compiler, firmware, systems, and application teams to ensure hardware/software co-design and successful product deployment.
  • Manage relationships and technical execution with foundries, OSATs, IP vendors, EDA vendors, and ASIC/design service providers.
  • Lead technical discussions involving process technology, IP selection, packaging, manufacturing, test, yield, cost, and supply-chain considerations.
  • Support silicon bring-up, characterization, debug, qualification, and transition into volume production.
  • Communicate architecture decisions, technical status, risks, schedules, and recommendations to engineering leadership and company executives.
  • Mentor engineers and technical leads and help build a hardware engineering organization.

Desired Qualifications

  • Experience developing AI/ML accelerators, GPUs, NPUs, CPUs, DSPs, or other high-performance compute architectures.
  • Knowledge of neural-network workloads and architectural considerations involved in accelerating modern AI models.
  • Experience with hardware/software co-design, including interaction with compilers, runtimes, firmware, and performance modeling.
  • Experience designing advanced memory hierarchies and working with SRAM, LPDDR, HBM, or other high-bandwidth memory technologies.
  • Experience with advanced semiconductor process nodes and the technical and economic tradeoffs of process-node selection.
  • Experience with advanced packaging, chiplets, 2.5D/3D integration, or die-stacking technologies.
  • Familiarity with PCIe, CXL, LPDDR, HBM, or other high-speed chip interfaces.
  • Experience selecting and integrating third-party semiconductor IP.
  • Experience managing outsourced RTL-to-GDS or turnkey ASIC development programs.
  • Experience working directly with foundries and major OSATs.
  • Understanding of semiconductor manufacturing, packaging, test, yield, reliability, and production cost.
  • Experience taking a semiconductor product from early architecture through production and volume shipment.
  • Previous experience building or leading hardware teams in a startup or other fast-paced engineering environment.

About the Company

MemryX

Edge AI processing accelerator chips

MemryX makes AI accelerator chips for edge AI. Its MX3 chip uses a configurable native dataflow architecture and in-memory computing to run AI models without needing manual tuning or retraining, and it can be scaled by adding chiplets to increase performance or reduce latency. The system minimizes data movement, allowing a single software stack to run multiple models across multiple chips efficiently. A distinguishing feature is its DRAM-like integration that simplifies deployment and its ability to support new hardware and AI models with the same software, plus a PC-ready AI accelerator card demonstrated in Lenovo ThinkCentre PCs. MemryX’s goal is to expand edge AI capabilities by providing a scalable, easy-to-use hardware-software stack that lowers barriers to deploying AI at the edge and into consumer/enterprise PCs by selling MX3 chips.

Company size
11-50
Company stage
Series B
Total funding
$52M
Headquarters
Ann Arbor, MI
Founded
2019

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