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PFN and Tenstorrent win NEDO xPU research project. Japan's Preferred Networks and AI-chip developer Tenstorrent have been selected for a five-year Japanese government-backed research project to develop an advanced computing platform that combines chiplets, photonics-electronics integration and advanced packaging. The companies will work on an extensible processing unit, or xPU, architecture under a program administered by Japan's New Energy and Industrial Technology Development Organization. NEDO announced the selected implementation structure on October 20, 2026, under its post-5G information and communications infrastructure initiative. Project divides work across AI and CPU chiplets. Preferred Networks will lead development of AI chiplets, including designs that use three-dimensional memory stacking. Tenstorrent will develop open-architecture CPU chiplets with support for confidential-computing features, according to the joint announcement. The project aims to connect multiple specialized chiplets through photonics-electronics integration and advanced packaging. Optical links can move data with lower electrical losses over some distances than conventional copper connections, while chiplet designs allow processors, memory and interface components to be developed separately and assembled into a larger system. For AI systems, those approaches could help address bandwidth and power constraints created by rapidly growing models and data volumes. The work is still research and development, however, and the announcement did not disclose a commercialization timetable, target manufacturing process, foundry arrangement, prototype performance or funding amount. Universities and research institutes join the effort. The companies said the University of Tokyo, Kobe University, Toyo University, the Japan Agency for Marine-Earth Science and Technology, the Japan Atomic Energy Agency and Tenstorrent Japan will participate as subcontractors. The mix gives the project access to semiconductor, systems, security and scientific-computing expertise. Research workloads from marine science and nuclear-energy organizations could also provide demanding use cases for evaluating bandwidth, reliability and confidential-computing capabilities. NEDO lists the project period as up to 60 months. Selection under the program establishes the research framework but does not guarantee that a resulting processor will reach commercial production or win customers. Development will have to integrate components from multiple teams, demonstrate manufacturability and produce software that can use the hardware efficiently. Open architecture broadens the competitive angle. Tenstorrent designs AI accelerators and CPU cores based on the open RISC-V instruction set. Its role in the NEDO project extends that strategy into a Japanese research program focused on next-generation infrastructure and domestic technology capabilities. The selection follows Tenstorrent's October financing round, when the company raised $1.5 billion at a $6.2 billion post-money valuation. The fresh capital is intended to expand hardware, software and intellectual-property operations, but the NEDO collaboration is a separate research award and the companies did not link a specific portion of the funding to it. Preferred Networks has developed processors and computing systems for deep learning and other high-performance workloads. The Japanese company also works on software and industry applications, giving it experience across the stack that could help connect chiplet design choices with model and systems requirements. The project arrives as governments and technology companies seek alternatives to tightly integrated, proprietary AI-computing platforms. Chiplets and open instruction sets can give system builders more flexibility, but they shift more responsibility to interconnects, packaging, compilers and software compatibility.

Tenstorrent opens OCA chiplet harness beta under Apache 2.0 - unite.ai. Tenstorrent released the open source beta of the Open Chiplet Atlas (OCA) Harness on October 22, 2026, the company announced. The Harness is a chiplet design framework that turns the OCA interoperability architecture into reusable, deployable implementations. The OCA Specification defines the rules that let chiplets from different vendors work together across the software, system, protocol, transport, and physical layers. The Harness builds those rules into the infrastructure every chiplet needs: security, boot, system management, debug and test, and die-to-die integration. Tenstorrent said chiplet teams that use the Harness can lower non-recurring engineering (NRE) costs and integration risk, and spend more of their time on the application logic that sets their chiplet apart. "The OCA architecture gives chiplet designers the freedom to build without depending on a single vendor," said Wei-Han Lien, Chief CPU Architect and Senior Fellow at Tenstorrent. "The Harness gives teams a reference design that reduces integration complexity so they can focus on their core IP and launch custom silicon." Inside the beta release. The beta includes the complete Harness RTL along with three management subsystems. The OCA Security Processor serves as the chiplet's root of trust, providing secure boot, measurement, key management, and lifecycle control. The OCA System Management Controller (SMC) manages system bring-up, clocks, power, thermal, reset coordination, and telemetry, and implements the OCA-defined boot and configuration protocols that peer chiplets use. Debug and Test Ports (DTP) provide uniform cross-chiplet debug and test access, including JTAG and OCA cross-trigger support. The OCA System Management Unit (SMU) brings these subsystems together, and the OCA AoU implementation carries native AXI4 traffic over UCIe die-to-die links between chiplets. A C++/SystemC virtual platform lets teams start firmware development before RTL simulation or silicon. The tt-oca-harness repository on GitHub mirrors that structure: its hw/sys directory holds the smc, sep, smu, and dtp subsystems, hw/ip holds reusable IP blocks including jtag, uart, and cross_trigger, and hw/common holds shared primitives with TL-UL and AXI infrastructure plus the register flow. Contributors and partner statements. BOS Semiconductors contributed the original AXI-over-UCIe RTL, and lowRISC helped open source the Harness. VNChip Labs and Signaloid are OCA ecosystem partners with contributions in progress. Quang Le, VP of Engineering and Co-Founder at VNChip Labs, said the OCA ecosystem provides a common, proven foundation that can reduce development risk, accelerate time to silicon, and create a more level playing field for companies of all sizes. Signaloid CEO and Founder Phillip Stanley-Marbell described his company's product as a compute accelerator for computing with probability distributions. "By removing integration friction, the OCA Harness allows our accelerator IP to tap seamlessly into a thriving and open chiplet ecosystem," he said, adding that this makes it easier to integrate across a wide variety of complete systems and SiPs with lower NRE costs and faster time-to-market. The Open Chiplet Atlas Ecosystem. The Harness is one component of the broader Open Chiplet Atlas Ecosystem, which Tenstorrent launched on October 22, 2025, at an event in San Francisco. More than 50 partners were involved at launch, ranging from semiconductor companies and global conglomerates to academic institutions. Tenstorrent organizes that ecosystem around three pillars. The Architecture pillar is an open architecture defining chiplet interoperability across five layers: physical, transport, protocol, system, and software. The Harness pillar is the open-source, reusable design framework containing the non-application logic a chiplet needs, which Tenstorrent says lets designers focus on their own value-add while keeping their chiplets interoperable. The Compliance pillar covers pre-silicon verification and post-silicon validation, including a Golden Chiplet for testing and community Plugfests. Tenstorrent describes the OCA Architecture as modular, open-source, and ISA- and IP-neutral, with specifications and frameworks developed transparently and available on a royalty-free basis. Draft v0.7 of the OCA Architecture Specification was published for public review at the launch. Backers named at launch included AIDC, Axelera AI, BOS Semiconductors, LG, Preferred Networks, Rapidus, and VeriSilicon, along with research institutions such as the Barcelona Supercomputing Center. Licensing and availability. According to the repository README, the main repository is the entry point to a family of Tenstorrent-owned ecosystem repositories: tt-oca-harness-aou holds the AXI-over-UCIe Bridge (AoU) RTL; tt-oca-harness-model provides a virtual platform of the harness for rapid prototyping; and tt-oca-manifest defines the OCA boot manifest format and provides producer and consumer tooling for the secure boot images the SEP subsystem loads. The published documentation set comprises a Getting Started Guide covering setup, workflows, and contribution; a Technical Reference Manual covering architecture and registers; an Integrator Guide for integrating the OCA Harness into a chiplet design; a Programmer's Guide covering the register programming model and firmware interfaces; Application Notes; a verification dashboard that serves as a single entry point for the design-verification status of every OCA Harness IP and subsystem; and per-subsystem datasheets for the SMC, SEP, SMU, DTP, and AoU. The Harness code is licensed under the Apache License 2.0, with documentation and images under CC-BY-4.0, and contributions are accepted under Apache 2.0. Tenstorrent said it designed the beta for early adopters, integrators, and contributors. The full release is targeted for January 2027.