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d-Matrix

Delivers memory-integrated AI compute platforms

Senior Staff Inference Performance Engineer

Applied Machine LearningConfirmed live in the last 24 hours
Full-time$175k - $265k /yr

About the Job

Requirements

  • At least 8 years of hands-on performance or systems engineering, including resolving difficult regressions across multiple layers of a stack.
  • A track record of finding performance overhead through profiling in unfamiliar, sparsely documented systems; experience with a specific vendor stack or accelerator is not required.
  • Strong systems fundamentals, including Linux internals, NUMA, CPU pinning and cpusets, PCIe, memory and cache behavior, and network paths.
  • Experience running performance-sensitive workloads on Kubernetes, identifying latency or throughput costs from scheduler defaults, network overlays, or orchestration abstractions, and closing the performance gap.
  • Working knowledge of LLM inference serving, including batching, KV-cache, prefill/decode, quantization, and speculative decoding.
  • Proficiency in Python and C/C++ to instrument, debug, and patch code across the stack.
  • Ability to produce technical writing that hardware, firmware, or platform teams can act on without context from the candidate’s part of the stack.
  • Sound judgment about ownership, with examples of correctly handing off problems outside the candidate’s ownership.
  • Fluency with AI and agentic tools for investigation, code search, log triage, and drafting instrumentation, with discipline to verify output against real data.

Responsibilities

  • Diagnose performance problems across the full serving path, from orchestration—including scheduling, placement, networking, and autoscaling—to inference internals, including batching, KV-cache, prefill/decode, serving framework, driver and runtime, interconnect, host operating system and NUMA, and accelerator.
  • Isolate each problem to a specific layer and owner, then determine whether to fix it directly, route it to the owning team, or do both, using a workaround where appropriate and tracking the permanent fix.
  • Write minimal, reproducible problem statements for cross-stack findings so owning teams can act without repeating the investigation.
  • Protect throughput, latency, and stability targets for orchestrated workloads by finding and closing gaps against bare metal, such as placement overhead, non-performance power defaults, and extra network hops.
  • Assess requirements for scaling from single deployments to fleet operation, including routing, placement, and shared-resource contention.
  • Capture each workload’s node requirements, including CPU placement, memory and NUMA locality, and network path, in the orchestration layer’s configuration so performant deployment is the default.
  • Build lightweight telemetry and benchmarks that reach into prototype stacks to isolate or hand off problems.
  • Turn recurring investigations into playbooks and mentor engineers in the profiling-first method.

Desired Qualifications

  • Experience with LLM serving frameworks such as vLLM, SGLang, or TensorRT-LLM.
  • Hands-on experience building or tuning speculative decoding, disaggregated serving, or heterogeneous serving architectures.
  • Experience tuning KV-cache management, request and batch scheduling, or weight prefetch and residency in an LLM serving system.
  • GPU programming and profiling experience, such as CUDA, Nsight, or NCCL.
  • Experience with pre-production or bring-up hardware, or in organizations where root causes routinely cross team boundaries.
  • Rust experience.
  • Startup experience or comfort in environments where priorities shift quickly.

About the Company

d-Matrix

Delivers memory-integrated AI compute platforms

d-Matrix provides scalable AI compute platforms for large datacenters with a focus on energy efficiency. Its core offering, the digital in-memory compute (DIMC) engine, places compute directly in programmable memory and uses a fabric of low-power, modular chiplets plus software to optimize AI inference. It differentiates itself by combining memory-integrated computation with a modular, chiplet-based design that reduces power use and data movement for high-volume workloads. The goal is to help large datacenters run AI workloads more efficiently at scale through customizable, energy-efficient compute solutions.

Company size
201-500
Company stage
Series C
Total funding
$429M
Headquarters
Santa Clara, CA
Founded
2019

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