Principal ASIC Verification Engineer

Salary Range: 180000 to 220000 (Currency: USD) (Pay period: per-year-salary)

Responsibilities

Own block-to-chip verification plans, schedules, and signoff criteria; lead test development and execution.
Provide technical direction, mentor engineers, review test plans and code, and participate in candidate interviews.
Define contractor scope, milestones, and acceptance criteria; review deliverables and oversee integration and handoff.
Develop Python testbenches, reusable drivers, monitors, reference models, and scoreboards integrated with RTL simulators.
Implement tests, automate regressions, debug failures, and close coverage. Communicate verification status, unresolved defects, and tapeout risks.
Lead post-layout gate-level verification, including netlist preparation, SDF annotation, and timing-accurate simulation.
Verify test modes and patterns with DFT, design, and physical design teams; resolve timing and signoff issues.
Resolve requirements and interface issues with architecture, RTL, firmware, and hardware teams; support silicon bring-up and validation.
Perform other duties as assigned.

Experience & Education

Bachelor's degree in electrical engineering, computer engineering, computer science, or a related field, or equivalent experience.
10+ years of ASIC/SoC verification experience, with 15+ preferred.
Experience verifying multiple ASICs through tapeout and subsequent silicon evaluation, applying findings to improve verification.

Qualifications

Experience with block-to-chip verification of registers, data paths, and firmware interfaces.
Strong Python skills for reusable, object-oriented testbenches with constrained-random stimulus, simulation control, checkers, and coverage.
Ability to build behavioral models of mixed-signal blocks, including their digital interfaces and timing.
Experience turning design requirements into verification plans, writing SystemVerilog assertions, and closing functional and code coverage.
Hands-on post-P&R experience preparing netlists and cell/memory models, annotating SDF, and debugging timing simulations.
DFT verification experience with test modes and flows such as scan shift/capture, ATPG patterns, MBIST, or JTAG.
Strong RTL and waveform debugging skills, especially resets, clock domains, X propagation, and timing checks.
Proficiency with SystemVerilog/UVM, HDL debug tools, Linux, and version control.
Experience with regression automation, failure reproduction, and triage.

Preferred Qualifications

Technical leadership through ASIC tapeout, including mentoring engineers, leading reviews, coordinating verification work, and communicating risks.
Experience directing verification contractors, defining scope and acceptance criteria, and reviewing delivery against quality and schedule commitments.
Silicon bring-up or validation experience, including lab debug and correlating hardware failures with simulation.
Experience with formal verification, equivalence checking, CDC/RDC, lint, emulation, or FPGA prototyping.
Familiarity with real-time control, signal processing, or quantum hardware.