Design-for-Test Engineer

The Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) Signoff, as well as Power Integrity, IR drop, and Electromagnetic Compatibility (Power/IR/EM). The team also oversees tape-out, mass production, packaging, testing, and board-level verification. They collaborate closely with front-end chip teams across business units to drive R&D progress and mass production deployment for chip. Responsibilities - Responsible for DFT-related work in SoC chips, including Scan, MBIST, ATPG, Boundary Scan, IP test etc. - Collaborate closely with STA, physical design, and power engineers to debug and resolve DFT-related Timing/Power-IR problems. - Work in partnership with test engineers to bring up test vectors on silicon and ensure successful testing. Minimum Qualification(s) - Master's degree or above, majoring in Microelectronics, Electronics, Computer Science or related fields, with more than 2 years of DFT work experience. - Proficient in scripting skills (such as TCL, Perl, Python, etc.). - Skilled in using DFT EDA tools and mastering DFT principles and methods. Preferred Qualification(s) - Familiarity with synthesis/STA is preferred. - Good team spirit and a serious and responsible work attitude.