Design Verification Lead Engineer

<strong>Job Requirements </strong><br><p><strong>Job Summary:</strong></p><p>We are looking for a highly skilled and hands on Lead Engineer to lead and drive Subsystem/SOC Design Verification for an ARM based SoC Design.</p><p>Extensive experience in SV/UVM based SOC or IP Verification.</p><p> </p><p><strong>Key Responsibilities:</strong></p><ul><li>Own and delivery IP/Subsystem/SOC Testbench development, define Test plan, Test development & debug.</li><li>Strong knowledge in CPU based SOC architecture.</li><li>Develop and execute System Verilog/UVM Testbenches for SOC/IP Verification</li><li>Develop SV/UVM based SOC/IP Testbench & Implement and run directed, random, and constrained random tests</li><li>Analyze & Debug simulation failures across IP, interconnects , Subsystem & Top level, and work with RTL team for resolution.</li><li>Define Functional/Code/Assertion coverage metrics, sign-off checklist and drive to closure.</li></ul><br><br><strong>Work Experience </strong><br><p><strong>Required Skills:</strong></p><ul><li>5+ years of hands-on experience in IP/SOC Verification with Strong SOC Architecture knowledge</li><li>Proficiency in SV/UVM based testbench development and constrain random verification.</li><li>Familiarity with standard verification tools ( VCS, Xcelium) and debug environment</li><li>Scripting skills ( Python/Perl) </li><li>Strong debugging, analytical and problem-solving skills </li><li>Experience in two or more High-Speed Interface Verification ( PCIE/USB/Ethernet/DDR*)</li></ul><p><strong>Optional Preferred Skills</strong></p><ul><li>Exposure to Formal Verification or assertion-based verification.</li><li>Power aware verification ( UPF)</li><li>GLS & Xprop runs</li></ul><br><br>