Upscale AI

High-performance AI networking hardware and software

Senior / Staff Engineer - Serdes Analog/Mixed-Signal Design

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-timeSanta Clara, CA, USA$223k - $243k /yr

About the Job

Requirements

A B.S., M.S., or Ph.D. in Electrical Engineering or a related technical field.
Relevant experience in analog/mixed-signal integrated circuit design, high-speed circuit design, or semiconductor product development.
A solid understanding of transistor-level circuit design, circuit analysis, and analog/mixed-signal simulation.
Hands-on experience with SPICE-based simulators and standard integrated circuit design workflows.
Familiarity with scripting languages such as Python, MATLAB, or equivalent tools.
Strong analytical and problem-solving skills, along with communication and teamwork skills.

Responsibilities

Design, simulate, and optimize analog and mixed-signal circuits for next-generation high-speed SerDes and related IP.
Perform transistor-level circuit design, behavioral modeling, and performance analysis to meet power, performance, and area targets.
Develop simulation testbenches, analyze circuit behavior, and troubleshoot performance or convergence issues.
Collaborate with architecture, digital design, physical design, layout, and validation teams to drive design integration and closure.
Participate in design reviews, identify potential risks, and develop practical solutions to circuit-level problems.
Support physical implementation, post-layout verification, silicon characterization, and debug as needed.
Develop scripts and automation to improve simulation efficiency, design productivity, and data analysis.
Document design methodologies, simulation results, and technical findings.

Desired Qualifications

Experience developing high-speed SerDes, wireline transceivers, data converters, clocking circuits, or other analog/mixed-signal IP.
Experience developing AI-driven schematic or layout workflows.
Familiarity with advanced CMOS process technologies and their circuit-design challenges.
Experience with post-layout simulation, parasitic extraction, and circuit-performance optimization.
Exposure to silicon bring-up, characterization, and circuit debug.
Ability to independently own design tasks and drive them to completion.
Experience in one or more technical areas: Fractional-N PLL, LC-VCO, DTC/TDC, multi-modulus divider (MMD), phase interpolator, injection-locked oscillator, multi-phase clock generator, high-speed time-interleaved DAC and line driver, transimpedance amplifier, CTLE, PGA, high-speed voltage followers, time-interleaved SAR ADC, track-and-hold circuits, bandgap, PTAT, LDO, temperature sensor, charge pump, auto-zero comparator, or R2R DAC.

Salary Range: 223000 to 243000 (Currency: USD) (Pay period: per-year-salary)

Why join Upscale, Inc.

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $500M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard.

About the Role

Upscale AI is developing next-generation high-speed connectivity solutions for AI infrastructure and data centers. We are looking for talented analog and mixed-signal design engineers to develop advanced SerDes circuits and foundation IP for next-generation high-bandwidth, energy-efficient interconnects.

Responsibilities

Design, simulate, and optimize analog and mixed-signal circuits for next-generation high-speed SerDes and related IP.
Perform transistor-level circuit design, behavioral modeling, and performance analysis to meet demanding power, performance, and area targets.
Develop simulation testbenches, analyze circuit behavior, and troubleshoot performance or convergence issues.
Collaborate with architecture, digital design, physical design, layout, and validation teams to drive design integration and closure.
Participate in design reviews, identify potential risks, and develop practical solutions to challenging circuit-level problems.
Support physical implementation, post-layout verification, silicon characterization, and debug as needed.
Develop scripts and automation to improve simulation efficiency, design productivity, and data analysis.
Document design methodologies, simulation results, and technical findings.

Minimum Qualifications

B.S., M.S., or Ph.D. in Electrical Engineering or a related technical field.
Relevant experience in analog/mixed-signal IC design, high-speed circuit design, or semiconductor product development.
Solid understanding of transistor-level circuit design, circuit analysis, and analog/mixed-signal simulation.
Hands-on experience with SPICE-based simulators and standard IC design workflows.
Familiarity with scripting languages such as Python, MATLAB, or equivalent tools.
Strong analytical, problem-solving, communication, and teamwork skills.

Preferred Qualifications

Experience developing high-speed SerDes, wireline transceivers, data converters, clocking circuits, or other analog/mixed-signal IP.
Experience developing AI-driven schematic or layout workflows.
Familiarity with advanced CMOS process technologies and their circuit-design challenges.
Experience with post-layout simulation, parasitic extraction, and circuit-performance optimization.
Exposure to silicon bring-up, characterization, and circuit debug.
Ability to independently own design tasks and drive them to completion.
Experience in one or more of the following technical areas:

Fractional-N PLL, LC-VCO, DTC/TDC, multi-modulus divider (MMD).
Phase interpolator, injection-locked oscillator, multi-phase clock generator.
High-speed time-interleaved DAC and line driver.
Transimpedance amplifier, CTLE, PGA, high-speed voltage followers.
Time-interleaved SAR ADC, track-and-hold circuits.
Bandgap, PTAT, LDO, temperature sensor, charge pump, auto-zero comparator, R2R DAC.

We welcome engineers who enjoy solving challenging technical problems, learning new circuit architectures, and delivering innovative silicon solutions.

Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

Equal Opportunity

Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

Accessibility & Accommodations

We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at [email protected]—we’re happy to help. Note: This inbox is only for accommodation requests.

About the Company

Upscale AI

High-performance AI networking hardware and software

Upscale AI builds a full-stack, high-performance AI networking platform to scale up GPU compute. It designs purpose-built silicon chips and a software orchestration layer that connects thousands of GPUs into a single, unified compute engine. The system is optimized for the heavy data movement and bursty traffic of large language model training and inference, enabling fast, scalable AI workloads. Unlike traditional, vendor-driven networking stacks, Upscale AI offers open-standard networking powered by silicon and software, and participates in consortia like UEC and SONiC to ensure interoperability across different hardware environments. Its customers include global hyperscalers, AI-first enterprises, and sovereign cloud providers who need large-scale, interoperable AI clusters without lock-in. The company’s goal is to democratize AI infrastructure by delivering high-performance, open-standard solutions that let organizations build and operate massive AI clusters more efficiently.

Company size: 201-500
Company stage: Series A
Total funding: $490M
Headquarters: Santa Clara, CA
Founded: 2024

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