Omni Design Technologies

Licenses high-performance IP cores for SoCs

Verification Engineering Lead/Manager

Engineering LeadershipConfirmed live in the last 24 hours

Full-timeHyderabad, Telangana, IndiaNo salary listed

About the Job

Requirements

Design, develop, and deploy UVM-based testbenches for multicore, multithreaded processor subsystems, verifying and signing off performance, power, and functionality for mixed-signal systems-on-chip.
Have experience with chip-level testbench architecture and verification of systems-on-chip and chipsets using ARM or RISC-V processors and the listed AMBA, high-speed, peripheral, and mixed-signal interfaces.
Have strong knowledge of digital design and two or three of the listed areas: AMBA AHB/AXI/APB-based SoC architecture, ADC/DAC, PCIe, Ethernet, CAN, or LPDDR interfaces.
Have strong knowledge of Verilog, SystemVerilog, UVM, and C/C++.
Have experience using assertions, constrained-random generation, and functional and code coverage.
Know scripting languages such as Perl, Python, Tcl, and Linux shells for verification-methodology and flow automation.
Have analytical debugging skills.
Have a BS in Electrical Engineering and at least 3 years of experience, or an MS in Electrical Engineering and at least 1 year of experience.
Know at least one high-speed interface such as USB, MIPI, PCIe, Ethernet, or DisplayPort.
Know two or three peripheral interfaces such as SDIO, UART, I2S, I2C, PWM, or SPI.
Have experience managing a verification team.
Have strong knowledge of ASIC simulation tools and verification languages, including sign-off simulators and Verdi or Siloti.
Be fluent in verification languages such as UVM, OVM, SystemVerilog, Vera, or Verilog.
Have experience writing test plans and creating directed and random test cases.
Have strong scripting skills in Perl, Python, and Linux shells.
Be able to identify problems and provide solutions under tight schedule pressure.
Have strong analytical problem-solving skills and attention to detail.
Have an interest in filling gaps in product development as needed.
Have good written and verbal communication skills, technical documentation skills, and interpersonal skills; be self-motivated and self-starting.

Responsibilities

Lead system-on-chip and mixed-signal verification efforts and the verification team.
Build a capable verification team and manage team tasks to achieve tape-out on the agreed schedule and production with agreed-upon turns; target revision 0 silicon success.
Develop test plans and test cases, and sign them off.
Develop testbenches for AMS and FC simulations.
Apply UPF awareness in verification work.
Develop tests to achieve more than 95% simulation coverage.
Work with the design team to debug failures.
Integrate and run BIST and DFT gate-level simulations.
Measure code, line, and toggle coverage and other metrics.
Run daily and weekly regressions and publish results.
Be responsible for FC RTL and gate-level simulations.
Mentor and lead a team of verification engineers.
Work with systems and test engineering teams to help validate parts and release them to production.

The position involves designing, developing and deploying UVM based Testbenches for multi-core, multi-threaded processor subsystems with emphasis on verifying and signing off performance and power along with functionality for mixed signal SOC. The candidate should have worked on architecture of chip-level testbenches and verification of SoCs and chipsets with ARM/RISC-V processor technology and AMBA AHB/AXI/APB along with high-speed interfaces like PCIe, MIPI, USB, Ethernet, Mobile DDR and Quad/Octa-SPI and peripheral interfaces like SDIO, UART, I2S, I2C, PWM, QEI, CAN, Ethernet, PCIe, UCIe as well as Mixed Signal AMS simulation environment.

Role and Responsibilities

· Lead the SOC and Mixed signal verification team and efforts
· Build capable verification team and manage the tasks and the team to get to tape out on agreed upon schedule and to Production with Agreed upon turns. Revision 0 Silicon success is highly desired.
· Develop and signoff on test plans and test cases
· Strong knowledge of digital design and two or three of AMBA AHB/AXI/APB based SoC Architecture, ADC/DAC, PCIe, Ethernet, CAN, LPDDR interfaces.
· strong knowledge of Verilog, System Verilog, UVM, C/C++
· Experience in usage of assertions, constrained random generation, functional/code coverage
· Knowledge of scripting languages like Perl, Python, TCL, Linux shells to achieve automation of verification methodologies and flows
· Analytical debugging skills
· Excellent team building and management skills

Qualifications and Skills

· BS in EE with 3+ years of experience or MS in EE with 1+ year experience
· Knowledge of at least one of high-speed interfaces like USB, MIPI, PCIe, Ethernet, DP,
· Knowledge of two or three of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, SPI
· Experience managing a verification team
· Strong knowledge with ASIC Simulation Tool & Verification Language: all sign-off simulators, Verdi/Siloti
· Fluent in verification languages such as UVM/OVM/System Verilog, Vera, Verilog
· Experience in writing Test-plans and creating directed and random test cases
· Strong scripting skills in Perl, Python, Linux shells etc.
· Strong problem-solving skill to quickly identify and provide solution under tight schedule pressure
· Strong analytical problem solving and attention to details
· Team player with interest in filing up gaps in product development as needed
· Good written and verbal communication skills
· Good technical documentation skills
· Good interpersonal skills, self-motivated, self-starter

Expectations

Develop the Test benchses for AMS and FC simulations
Be UPF Aware.
Develop the tests to get 95+% coverage for the simulations
Work with Design team to debug any failures
Integrate and run the BIST and DFT gate level sims.
Do code, line and toggle coverage and other metrics.
Run daily and weekly regressions and publish results
Responsible for FC RTL, Gate level simulations
Be a mentor and lead a team of Verification engineers
Work with Systems and Test engineering team to help validate the parts and release them to production

About the Company

Omni Design Technologies

Licenses high-performance IP cores for SoCs

Omni Design Technologies delivers high-performance, ultra-low power IP cores for mixed-signal SoCs that power devices across 5G, LiDAR, automotive networks, AI, image sensing, and IoT. It develops and validates IP blocks and licenses them to chip makers, offering customization and support to ensure seamless integration into customer designs. The cores are designed to work on FinFET processes down to 28nm, with proven silicon such as gigasample low-power ADCs and DACs on TSMC 28nm. The company differentiates itself through validated, silicon-proven IP, deep collaboration with customers and partners (e.g., LeddarTech, MegaChips), and a global design footprint (new Fort Collins design center). Its goal is to enable customers to build sophisticated, power-efficient, mixed-signal SoCs quickly by providing ready-to-license IP plus engineering services that fit their specific needs.

Company size: 51-200
Company stage: Series A
Total funding: $35M
Headquarters: Milpitas, CA
Founded: 2015

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