Design Verification Engineer for DFT

<h2>Meet the Team</h2><p>We are a leading Design for Test (DFT) group, delivering end-to-end solutions for Cisco’s flagship products, including Cisco Silicon One. Our chips are strategically placed in critical AI infrastructure, powering next-generation network devices and supporting advanced AI workloads.</p><p>We push the boundaries of technology by developing innovative DFT solutions that drive industry-leading programmability, scalability, test quality, and performance. Our team operates in a hybrid model, with three days a week in the office in Midtown Tel Aviv or Caesarea, fostering collaboration and technical excellence in a startup-like atmosphere within a stable, global corporation.</p><p><b>Role Focus: </b>We are looking for an experienced Design Verification engineer to join our DFT team and help establish and grow DFT DV activity in the Cisco SiliconOne DFT team. This role is relevant for engineers with experience in DV roles, either in DFT DV or in other verification domains, who are interested in becoming familiar with DFT design, verification methodologies, and the challenges of validating testability features in advanced silicon.</p><h2>Your Impact</h2><p>Lead and drive DFT verification activities within the Cisco SiliconOne DFT team.</p><p>Develop verification plans, environments, checkers, assertions, and coverage models for DFT features.</p><p>Verify DFT architecture and implementation in close collaboration with DFT, design, architecture, and verification teams.</p><p>Work on verification of scan, MBIST, IJTAG/JTAG, test access mechanisms, DFT controllers, and related SoC-level test features.</p><p>Debug complex pre-silicon issues across RTL, verification environments, and DFT logic.</p><p>Contribute to scalable methodologies, reusable verification components, and best practices for DFT DV.</p><p>Help bridge between general DV methodologies and DFT-specific design and verification needs.</p><h2>Minimum Qualifications</h2><ul><li><a href="https://b.sc/" target="_blank">B.Sc</a>. or <a href="https://m.sc/" target="_blank">M.Sc</a>. in Electrical Engineering, Computer Engineering, or a related field.</li><li>5+ years of experience in design verification roles.</li><li>Strong experience with SystemVerilog and UVM-based verification environments.</li><li>Experience developing verification plans, coverage models, assertions, and debug flows.</li><li>Strong communication skills and ability to work closely with cross-functional teams.</li><li>Motivation to learn DFT concepts and become a key contributor in the DFT DV domain.</li></ul><h2>Preferred Qualifications</h2><ul><li>Familiarity with DFT concepts such as scan insertion, memory BIST, ATPG, boundary scan, and silicon test flows.</li><li>Experience with complex SoC verification, networking silicon, or high-performance AI-driven silicon.</li><li>System-level understanding of large-scale chip architecture and integration.</li><li>Ability to build new methodologies and establish verification activity from the ground up.</li><li>High attention to detail, ownership mindset, and willingness to grow into new technical domains.</li></ul><p></p><h1>Why Cisco? </h1><p>At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.</p><p>Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. </p><p>We are Cisco, and our power starts with you. </p><p></p>