A

AMD

Designs chips for computers and AI systems

Lead HPC & AI Infrastructure Architect

Platform EngineeringConfirmed live in the last 24 hours
Full-timeSan Jose, CA, USANo salary listedIn-person

About the Job

Requirements

  • Significant experience in infrastructure, cloud engineering, or distributed systems, including demonstrated experience designing and delivering production HPC or GPU platforms; equivalent practical experience is welcome.
  • Experience leading large-scale cluster deployments involving hundreds of nodes, substantial multi-GPU environments, or systems of comparable technical complexity, with measurable improvements in workload performance, reliability, utilization, or cost.
  • Experience with a major cloud platform such as Azure, OCI, or AWS, including integration between cloud and on-premises systems. Familiarity with specialized GPU providers such as Crusoe or TensorWave is beneficial.
  • Strong Linux troubleshooting skills across CPU/NUMA topology, PCIe, GPU connectivity, drivers, virtualization, containers, and distributed runtime environments.
  • Hands-on experience with Slurm scheduling and resource governance, plus Kubernetes or comparable orchestration experience. Understanding of MPI, distributed training, collective communication, and AI inference infrastructure.
  • Experience with GPU computing platforms and distributed AI workloads. Experience with AMD Instinct GPUs, ROCm, RCCL, and multi-node PyTorch workloads, including compatibility validation and performance troubleshooting, is particularly relevant.
  • HPC networking and storage experience, including RDMA, RoCE or InfiniBand, topology and oversubscription tradeoffs, parallel I/O, data placement, checkpointing, and enterprise connectivity.
  • Experience with parallel and shared storage technologies such as Lustre, IBM Storage Scale, BeeGFS, NFS, VAST, or comparable technologies, as well as object storage and cluster acceptance benchmarking.
  • Experience with Terraform or equivalent infrastructure as code, Ansible or comparable configuration management, Python or Bash, and Git-based CI/CD. Familiarity with Azure CycleCloud, AWS ParallelCluster, or comparable cluster provisioning frameworks is beneficial.
  • Experience implementing observability and SRE practices using Prometheus, Grafana, or comparable technologies, including secure access, resource controls, fault recovery, and production readiness.
  • Ability to lead cross-functional technical work, clearly communicate architecture decisions and tradeoffs, and guide projects from requirements through production acceptance.
  • Experience coordinating with hardware and data center teams on rack power, liquid cooling, facility capacity, and other physical constraints affecting GPU platform design.
  • Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience.

Responsibilities

  • Lead the HPC and AI infrastructure roadmap, reference architectures, and standards for CPU/GPU clusters. Define workload placement across bare metal, virtual machines, Slurm, and Kubernetes.
  • Lead designs covering CPU/NUMA and GPU topology, accelerator interconnects, networking, storage, and identity. Establish validated hardware, firmware, driver, and runtime baselines.
  • Architect RDMA-capable fabrics and storage tiers. Validate collective communication, parallel I/O, dataset delivery, and checkpoint performance at target scale.
  • Design resource sharing through Slurm accounting, fair-share, quotas, QoS, preemption, and tenant isolation. Enable reproducible environments, self-service onboarding, and inference capacity planning.
  • Standardize provisioning, configuration, and fleet upgrades through infrastructure as code, automation, and CI/CD; manage images, containers, and configuration drift.
  • Define production acceptance criteria, service-level objectives, and fleet observability. Partner with SRE teams on fault isolation, job recovery, checkpoint/restart, incident analysis, and capacity planning.
  • Benchmark HPC and distributed AI workloads; improve scaling efficiency, throughput, inference latency, GPU utilization, reliability, and cost efficiency through bottleneck analysis.
  • Incorporate federated identity, least-privilege access, tenant and network isolation, secrets management, controlled container privileges, audit logging, and vulnerability management into platform designs.
  • Lead architecture reviews, proofs of concept, provider evaluations, and complex technical problem solving. Document decisions and tradeoffs, mentor engineers, and align delivery with stakeholders and infrastructure partners.

Desired Qualifications

  • Hands-on experience with AMD Instinct GPUs, ROCm, RCCL, and multi-node PyTorch workloads, including compatibility validation, benchmarking, and performance troubleshooting.
  • Experience with Azure, OCI, Crusoe, TensorWave, or comparable GPU environments and cluster provisioning frameworks such as Azure CycleCloud or AWS ParallelCluster.
  • Experience with Lustre, IBM Storage Scale, BeeGFS, VAST, or comparable high-performance storage platforms, plus network, storage, and collective communication benchmarks used for cluster acceptance.
  • Experience with LLM serving platforms such as vLLM or SGLang, model parallelism, inference capacity planning, and usage accounting or cost allocation.
  • Understanding of rack power, liquid cooling, and facility capacity constraints, with experience coordinating platform requirements with hardware and data center teams.

About the Company

AMD

Designs chips for computers and AI systems

AMD designs processors, graphics chips and AI accelerators for computer makers, cloud operators and businesses that build electronic devices. Its Ryzen processors power personal computers, while EPYC processors handle work in data centers and Radeon chips render graphics. Instinct accelerators run AI models, paired with software that developers use to train models and put them into production. AMD sells chips and related computing systems through equipment makers, distributors and retail channels, and contracts with outside foundries to fabricate its semiconductor designs. It was founded in 1969 and has its headquarters in Santa Clara, California.

Company size
10,001+
Company stage
IPO
Headquarters
Santa Clara, CA
Founded
1969

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