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Astera Labs

Designs chips that connect data center systems

Senior Embedded Software Engineer - Ethernet Retimers

Embedded EngineeringConfirmed live in the last 24 hours
Full-timeSan Jose, CA, USAIn-person

About the Job

Requirements

  • A bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • At least 5 years of experience in firmware development or embedded systems engineering.
  • Hands-on experience with Ethernet at the system or device level, including Layer 1 PHY, SERDES, retimers, gearboxes, network interface cards, switches, or related devices.
  • Solid embedded C and C++ skills and comfort working in a firmware codebase on real hardware.
  • Ability to debug across the hardware/software boundary, including register accesses, embedded software development kits, link state machines, PHY telemetry, and debug print logs.
  • Familiarity with Linux development tools, including gcc/clang, make, bash, gdb, and git.
  • Strong communication skills and comfort working in a fast-moving environment where problems may not have a clean solution.

Responsibilities

  • Work directly with the system validation team to debug firmware behavior across different Ethernet configurations, link states, and failure modes.
  • Investigate and fix firmware issues in embedded C, using understanding of how Layer 1 PHY, SERDES, FEC/PCS, MAC, and retimer components interact.
  • Serve as the connection between firmware and system validation teams, triaging issues and driving them to resolution without long handoff loops.
  • Support customer bring-up and integration activities, including triaging field issues and coordinating fixes with internal teams.
  • Partner with field applications engineers to diagnose and resolve deployment issues.
  • Contribute to firmware feature development for SERDES configuration, link training, equalization, and diagnostics.
  • Partner with SoC, field applications, and platform teams across the full product lifecycle.
  • Help bring new Taurus products from initial silicon bring-up through customer deployment.

Desired Qualifications

  • Experience with switch or network interface card management software, SAI, or OpenBMC.
  • Knowledge of PMA, FEC, or other PHY-layer subsystems beyond SERDES.
  • Background with retimer or gearbox firmware or software development kit/API development.
  • Python scripting for debugging, test automation, or data analysis.
  • Experience with lab equipment such as BERT, oscilloscopes, Viavi, Lecroy, Exfo, Keysight, or Tektronix.
  • Understanding of signal integrity, including equalization, jitter, eye diagrams, and link margin.
  • Prior experience mentoring engineers or leading debug efforts across teams.

About the Company

Astera Labs

Designs chips that connect data center systems

Astera Labs designs chips and hardware modules that move data between processors, memory and accelerators in data centers. Its customers include cloud providers, chip vendors and equipment makers building servers and large computing clusters for AI and other workloads. Retimers restore signal quality, switches connect devices and memory controllers expand the memory available to computing systems, while COSMOS software monitors and manages these links. The company sells its products directly and through distributors, using outside manufacturers to fabricate and assemble its hardware. Astera Labs was founded in 2017 and is headquartered in San Jose, California.

Company size
501-1,000
Company stage
IPO
Headquarters
San Jose, CA
Founded
2017

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