Persimmons.ai

Generative AI inference accelerator for edge

Silicon Design Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-timeSan Jose, CA, USANo salary listed

About the Job

Requirements

A bachelor's or master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
At least 3 years of hands-on RTL-to-PD implementation experience, including taking designs from synthesis through tapeout on real silicon.
Experience with MAS and test-plan development, test implementation, and complex debugging across diverse IP blocks, SoCs, and system-level designs.
Strong skills in SystemVerilog, verification methodology, and C/C++ embedded code for processor validation.
Proficiency in SystemVerilog/Verilog and familiarity with Cadence and/or Synopsys synthesis and physical implementation toolchains, including associated quality and sign-off checks.
Strong command of static timing analysis and ability to write timing constraints from scratch based on RTL-level design understanding.
Experience developing and maintaining scripted, automated design flows.
Fluency with modern AI tools and workflows, such as using AI assistants for research, analysis, or productivity.

Responsibilities

Own RTL-to-PD handoff flows to physical-design partners, including synthesis, timing constraints, UPF, and static checks, ensuring designs meet quality, performance, power, and area targets.
Lead unit-level design execution and verification planning; collaborate with architecture, software, and design teams to develop MAS, execution, and test plans that meet SoC specifications.
Drive timing closure by authoring timing constraints based on RTL understanding, running static timing analysis, and resolving setup violations across complex multi-corner environments.
Execute floorplanning and physical implementation using Cadence/Synopsys tools, making decisions on macro placement and tool options to optimize power, performance, and area.
Build and maintain scripted, automated design flows that streamline synthesis, analysis, and sign-off, leveraging AI agents and modern automation tools to accelerate iteration and reduce manual work.
Collaborate with RTL design, DFT, and verification teams on frontend-to-backend handoffs, quality checks, and integration across the design hierarchy.
Contribute to post-design-verification activities including power analysis, CDC/RDC checks, UPF creation, formal verification, and DFT scan and MBIST integration as needed.

Desired Qualifications

Exposure to AI-assisted automation tools is a strong plus.

Silicon Design Engineer

Persimmons · San Jose, United States (Hybrid) · Full-time · Posted 2026-10-13

Workplace: hybrid

Description

Who we are:

Persimmons is building the infrastructure that will power the next decade of AI. Founded in 2023 by veteran technologists from the worlds of semiconductors, AI systems, and software innovation, We’re on a mission to enable smarter devices, more sustainable data centers, and entirely new applications the world hasn’t imagined yet.

Why join us:

We’re growing fast and looking for bold thinkers, builders, and curious problem-solvers who want to push the limits of AI hardware and software. If you’re ready to join a world-class team and play a critical role in making a global impact - we want to talk to you.

What you'll do:

As a Persimmons Silicon Design Engineer, you will be responsible for high quality RTL drops to our PD Partners of next-generation AI silicon. Your primary duties and responsibilities include:

Own RTL-to-PD handoff flows to PD Partners, including synthesis, timing constraints, upf and static checks. Ensuring designs meet quality, performance, power & area targets.
Lead unit level design execution & verification planning. Collaborate with architecture, software, and design teams to develop MAS, execution & test plans that ensures we meet SoC specifications.
Drive timing closure by authoring precise timing constraints from RTL understanding, running static timing analysis & resolving setup violations across complex multi-corner environments.
Execute floorplanning and physical implementation using Cadence/Synopsys tools, making informed decisions on macro placement & tool options to optimize PPA.
Build and maintain scripted, automated design flows that streamline synthesis, analysis, and sign-off processes—leveraging AI agents and modern automation tools to accelerate iteration and reduce manual overhead.
Collaborate closely with RTL design, DFT, and verification teams to manage frontend-to-backend handoffs, enforce quality checks, and ensure seamless integration across the design hierarchy.
Contribute to advanced post DV design activities including power analysis, CDC/RDC checks, UPF creation, formal verification, and DFT scan and MBIST integration as scope demands.

Requirements

What You Bring To The Table:

Educational Foundation: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
Proven Experience: 3+ years of hands-on RTL-to-PD implementation experience, with demonstrated success taking designs from synthesis through tapeout on real silicon.
Experience with MAS & test plan development, test implementation, and complex debugging across diverse IP blocks, SoCs, and system-level designs.
Strong skills in SystemVerilog, Verification methodology, and C/C++ embedded code for processors validation.
Technical Mastery: Proficiency in SystemVerilog/Verilog and deep familiarity with Cadence and/or Synopsys synthesis and physical implementation toolchains, including all associated quality and sign-off checks.
Specialized Expertise: Strong command of static timing analysis and the ability to write timing constraints from scratch based on RTL-level design understanding.
Flow Innovation: Experience developing and maintaining scripted, automated design flows; exposure to AI-assisted automation tools is a strong plus.
Demonstrated fluency with modern AI tools and workflows (e.g., leveraging AI assistants for research, analysis, or productivity).

Benefits

Competitive salary and benefits package
Flexible PTO
401k

Please note: Our organization does not accept unsolicited candidate submissions from external recruiters or agencies. Any such submissions, regardless of form (including but not limited to email, direct messaging, or social media), shall be deemed voluntary and shall not create any express or implied obligation on the part of the organization to pay any fees, commissions, or other compensation. Direct contact of employees, officers, or board members regarding employment opportunities is strictly prohibited and will not receive a response.

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About the Company

Persimmons.ai

Generative AI inference accelerator for edge

Persimmons.ai designs and builds a flexible, low-power generative AI inference system as a fabless semiconductor company. Its main product is a generative AI accelerator and accompanying software stack for AI inference, targeting high compute density and scalable performance across both edge devices and data centers. The system combines hardware (chiplet-based accelerator architecture), algorithms, and compiler technology to optimize generative AI workloads efficiently. Unlike traditional single-die accelerators, Persimmons emphasizes a scalable, full-stack approach that integrates hardware, software, and compilers to maximize inference throughput per watt from edge to high-performance computing (HPC) environments. The company aims to deliver a practical solution that enables dense, energy-efficient AI inference at scale for diverse deployment locations and workloads.

Company size: 11-50
Company stage: Not listed
Total funding: Not listed
Headquarters: San Jose, CA
Founded: 2023

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