ASIC Digital Design Staff Engineer
Synopsys
ASIC Digital Design Staff Engineer
Synopsys
EDA software for chip design
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You are an experienced Digital Verification engineer who enjoys solving complex verification challenges in high-speed digital designs. You bring a strong understanding of ASIC design and verification methodologies and have hands-on experience verifying designs involving high-speed interface protocols. You are comfortable working with complex RTL designs, developing verification environments, debugging failures, and driving verification to closure. Experience with PCI/PCIe or USB interfaces is particularly valuable, with USB experience highly preferred for this position.
With approximately 5–6 years of relevant experience, you are ready to take ownership of verification activities while collaborating closely with design engineers and other technical teams.
What You'll Be Doing
Develop and execute verification strategies for complex ASIC and digital IP designs.
Build, enhance, and maintain verification environments for high-speed digital interfaces.
Develop test plans, test cases, stimulus, checkers, and coverage models to achieve verification objectives.
Verify functionality of designs involving high-speed protocols, particularly PCI/PCIe and USB.
Debug simulation failures and collaborate with RTL design engineers to identify and resolve functional issues.
Analyze functional and code coverage and drive verification toward closure.
Participate in design and verification reviews and contribute to improving verification quality and efficiency.
Take ownership of assigned verification areas from planning through final verification closure.
The Impact You Will Have
Help ensure the functional quality and robustness of complex ASIC and digital IP designs.
Contribute to successful verification and delivery of high-speed interface technologies.
Identify design issues earlier in the development lifecycle through thorough verification and debugging.
Improve overall verification coverage and quality through systematic test development and coverage analysis.
Collaborate with engineering teams to help deliver reliable, high-quality semiconductor IP.
What You'll Need
Approximately 5–6 years of relevant experience in ASIC/Digital Verification.
Strong knowledge of ASIC and digital design verification concepts.
Hands-on experience verifying high-speed protocols/interfaces.
Experience with PCI/PCIe and/or USB, with USB experience highly preferred.
Experience developing and maintaining verification environments for complex digital designs.
Strong debugging and problem-solving skills for identifying RTL and verification-environment issues.
Understanding of test planning, functional verification, coverage analysis, and verification closure.
Experience or exposure to AI assisted verification methodology would be a plus.
Ability to work effectively with design and verification teams throughout the development lifecycle.
Position is open for BLR/NCR.
Who You Are
You approach complex verification problems methodically and take ownership through resolution.
You are comfortable digging into RTL, waveforms, logs, and verification results to understand failures.
You communicate technical issues clearly and collaborate effectively with design and verification engineers.
You pay close attention to quality and coverage rather than simply getting tests to pass.
You can work independently while contributing effectively within a broader engineering team.
You are curious, technically driven, and comfortable learning new interfaces and verification challenges.
The Team You'll Be Part Of
You will be part of a digital engineering team working on ASIC and high-speed interface technologies. The role involves close collaboration with design and verification engineers to develop robust verification environments, identify functional issues, and drive designs toward verification closure.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
Synopsys provides software tools and services for electronic design automation (EDA), helping engineers design, simulate, verify, and optimize semiconductor chips and systems. Its products cover the full design flow, including RTL-to-gating synthesis, place-and-route, timing analysis, verification, and silicon validation, as well as software integrity solutions and hardware-assisted verification. Engineers use these tools to model, simulate, and validate complex chip designs before manufacturing, reducing bugs and improving performance. Compared with many competitors, Synopsys differentiates itself through its broad, end-to-end design toolchain, large ecosystem of IP and integration with simulation and modeling capabilities gained from its 2025 merger with ANSYS, and its global scale and support. The company aims to help designers push the boundaries of chip and system performance, accelerate time-to-market, and enable silicon-to-systems design across a wide range of industries.
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