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Monolithic Power Systems

Fabless semiconductor designer of power solutions

Senior Layout Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeNo salary listedIn-person

About the Job

Requirements

  • At least 5 years of layout experience in analog and/or mixed-signal circuit design.
  • Ability to plan chips, estimate die size, and estimate project schedules.
  • Ability to resolve design rule check and layout versus schematic verification data and independently tape out chips.
  • Familiarity with the fundamentals of analog processes.

Responsibilities

  • Estimate layout schedules.
  • Place devices at the block level according to matching requirements.
  • Implement blocks at the top level.
  • Match signals and apply shielding techniques to sensitive nets.
  • Apply pad and electrostatic discharge rules, and route and connect pads.
  • Perform database design rule check and layout versus schematic verifications.
  • Tape out chips in accordance with the company’s tapeout procedure.

Desired Qualifications

  • Familiarity with Cadence and/or Virtuoso tools.

About the Company

Monolithic Power Systems

Fabless semiconductor designer of power solutions

Monolithic Power Systems designs and sells high-performance power management solutions and analog integrated circuits (ICs) for a variety of markets, including industrial, telecom, cloud computing, automotive, and consumer electronics. It operates as a fabless company, outsourcing semiconductor manufacturing to third-party foundries. Its products are compact, highly integrated power-management ICs that help end systems reduce energy consumption and improve efficiency. MPS primarily sells directly to OEMs and ODMs and through distributors and resellers. By focusing on proprietary process technology and design, MPS differentiates itself via efficient, easy-to-use power solutions that enable customers to lower total system power. The company’s goal is to provide reliable, energy-efficient power management components that enable customers to improve performance while minimizing power usage across diverse applications.

Company size
1,001-5,000
Company stage
IPO
Headquarters
West Palm Beach, FL
Founded
1997

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