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Broadcom

Designs chips and software for data centers

Design Verification Engineer

Hardware Validation & TestingConfirmed live in the last 24 hours
Full-timeIn-person

About the Job

Requirements

  • At least 12 years of experience with verification concepts and architectures for complex digital and mixed-signal circuits.
  • Experience verifying designs at the block and system levels.
  • Experience with complex digital and mixed-signal circuits, including PLL, DLL, ADC, and DAC.
  • Experience debugging RTL and gate-level netlists and analyzing schematic diagrams of analog and mixed-signal circuits.
  • Experience using SystemVerilog and advanced verification concepts and methodologies, including UVM and SVA.
  • Experience with Synopsys, Cadence, and Mentor simulation tools.
  • Ability to plan and deploy complex, reusable, and scalable verification environments.
  • Experience with Perl, Python, Tcl, or other scripting languages.
  • Experience with version control systems such as DesignSync and Git.
  • Strong writing, grammar, and verbal communication skills.
  • Ability to solve problems and develop and employ automated processes where applicable.
  • Ability to work independently and in a global team and dynamic environment in a highly visible role.
  • Ability to learn and adapt to new tools and methodologies.
  • Legal authorization to work in the United States.
  • A BS in Electrical Engineering or Computer Engineering and at least 12 years of related experience, or an MS in Electrical Engineering or Computer Engineering and at least 10 years of related experience.

Responsibilities

  • Perform modeling and verification activities related to complex digital and mixed-signal IP blocks used in ASIC developments.
  • Define verification plans and environment architecture.
  • Develop test cases and testbench components.
  • Perform coverage analysis and closure, and debug verification issues.
  • Work with emulation and FPGA prototyping platforms as needed, and lead efforts to evaluate and adopt advanced verification methodologies and flows.
  • Develop functional models to facilitate block-, system-, and ASIC-level verification.
  • Work closely with design teams and EDA vendors to accomplish modeling and verification tasks.
  • Design verification components, including UVM agents, checkers, and behavioral models.
  • Develop random and directed test cases and SystemVerilog assertions to implement and achieve coverage goals.
  • Analyze and debug simulation failures at the RTL and gate level.
  • Analyze RTL, gate-level netlists, and SDF in the verification context.

Desired Qualifications

  • Expertise in hardware design and debug.
  • Experience with emulation platforms such as Palladium, Veloce, or Zebu, and FPGA platforms such as Xilinx.
  • Formal verification concepts or experience.
  • Experience verifying an iJTAG network using ICL and PDL in the Tessent tool.
  • Experience with co-simulation.

About the Company

Broadcom

Designs chips and software for data centers

Broadcom designs chips and sells infrastructure software for the companies that run large data centers, telecom networks and corporate IT. Its custom AI processors, built with cloud companies, and its Ethernet switch chips move and process data inside the computer clusters that train AI models. The chip business also makes parts for broadband, wireless, storage and industrial equipment, sold to device makers and cloud operators, while VMware software lets businesses run private clouds and is sold by subscription. Broadcom took its current form in 2016, when Avago Technologies, formed in 2005 from Agilent's chip unit, bought Broadcom Corporation, and it is based in Palo Alto, California.

Company size
10,001+
Company stage
IPO
Headquarters
Palo Alto, CA
Founded
2005

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