CScale

Optical interconnects for large-scale AI infrastructure

Static Timing Analysis Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-timeBengaluru, Karnataka, IndiaNo salary listedIn-person

About the Job

Requirements

Eight to twelve years of hands-on experience in synthesis, static timing analysis, constraint development and validation, timing signoff, and engineering change order implementation.
Strong grasp of timing fundamentals, including setup and hold checks, clock definitions, SDC constraints, and timing exceptions.
Practical experience with industry-standard static timing analysis tools such as Synopsys PrimeTime or Cadence Tempus.
Understanding of the physical design flow, including placement, clock tree synthesis, and routing, and its impact on timing.
Exposure to timing analysis across multiple modes and corners (MMMC).
Proficiency in Tcl, Perl, or Python for automation and report analysis.
Strong analytical and debugging skills.
Ability to work across Physical Design, RTL, DFT, and constraints teams.
Excellent communication and problem-solving skills.

Responsibilities

Develop the synthesis and static timing analysis flow using PrimeTime or Tempus.
Develop and validate timing constraints (SDC) for functional and test modes, including DFT, scan, and MBIST.
Run top-level, subsystem, and block-level timing analysis and drive designs to timing closure.
Debug setup and hold violations, and work with Physical Design and Design teams to resolve them.
Generate, implement, and validate timing ECOs, and confirm each fix holds across all modes and corners.
Produce and review timing reports across modes and corners, and flag risks and trends to the team.
Support timing signoff and root-cause timing and constraint issues through tape-out.

Desired Qualifications

Experience with advanced process nodes.

CScale is building the interconnect for gigawatt-scale AI. As AI scale-up moves toward deployments spanning thousands of accelerators and dozens of racks, the network needs to deliver high bandwidth, predictable low latency, and continuous communication. CScale is building integrated optical interconnect designed for this new scale, enabling accelerators to work together like a single, much larger computer. But at this scale, performance is only part of the challenge. Optical failures are inevitable, and the system needs to keep running. CScale is designing the interconnect for continuity.Lasers will fail. Compute shouldn’t.The ambition is simple:Build AI interconnect you can take for granted.CScale came out of stealth in September 2026 with $145 million in Series C funding, bringing total funding to $188 million.

Key Responsibilities:

Develop the SYNTH & STA flow using PrimeTime/Tempus.
Develop and validate timing constraints (SDC) for functional and test modes (DFT, scan, MBIST).
Run Top-Level/Sub-System/Block level timing analysis and drive designs to timing closure.
Debug setup and hold violations, and work with Physical Design and Design teams to fix them.
Generate, implement and validate timing ECOs, and confirm each fix holds across all modes and corners.
Produce and review timing reports across modes and corners, and flag risks and trends to the team.
Support timing signoff, and root-cause timing and constraint issues through tape-out.

Requirements:

8-12 years of hands-on experience in SYNTH, STA, constraint development & validation, timing signoff and ECO implementation.
Strong grasp of timing fundamentals, including setup/hold checks, clock definitions, SDC constraints and timing exceptions.
Practical experience with industry-standard STA tools (Synopsys PrimeTime or Cadence Tempus).
Understanding of the physical design flow (placement, clock tree synthesis, routing) and its impact on timing.
Exposure to timing analysis across multiple modes and corners (MMMC).
Proficiency in Tcl, Perl or Python for automation and report analysis.
Strong analytical and debugging skills.
Proven ability to work across Physical Design, RTL, DFT and constraints teams.
Excellent communication and problem-solving skills.
Experience with advanced process nodes is a plus.

About the Company

CScale

Optical interconnects for large-scale AI infrastructure

CScale builds optical interconnects for large-scale AI computing. Its integrated light engines power gigawatt-scale AI facilities by containing optical failures and keeping compute running across thousands of closely connected accelerators. The hardware provides high-bandwidth, ultra-low-latency optical links to connect accelerators across racks, making data movement between chips dependable for continuous AI workloads. Unlike many data-center components that rely on electronic signaling, CScale focuses on silicon photonics and photonic hardware to deliver scalable, reliable communication at scale. Founded in 2023 in Palo Alto, the company exited stealth in 2026 and has investors including NVIDIA and Intel Capital. Its goal is to enable uninterrupted AI training and inference across large AI infrastructure by delivering dependable optical interconnects that scale as data-center needs grow.

Company size: 51-200
Company stage: Series C
Total funding: $145M
Headquarters: Palo Alto, CA
Founded: 2023

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