DFT Engineer
Mirafra Technology
DFT Engineer
Mirafra Technology
Turnkey ASIC design and semiconductor engineering
Need knowledge of design for test (DFT) structures such as scan chains,
scan compression and verification concepts for test coverage (ATPG). Be
able to generate ATPG and analyze coverage results and how to extend or
optimize them. Need to know how to run gate simulation for to verify scan
patterns to demonstrate functionality.
Min Qualifications:
5 years experience in DFT in ASICs
10 years experience in DFT for large scale ASICs. Experience with Mentor
Graphics DFT tools.
All your information will be kept confidential according to EEO guidelines.
Turnkey ASIC design and semiconductor engineering
Mirafra Technologies delivers end-to-end turnkey ASIC design and semiconductor engineering services to help global tech companies move from concept to silicon to system. It covers the full lifecycle: architecture, design, verification, physical implementation, package/board design, embedded software, post-silicon validation, test and product engineering, and system solutions. With 2,200+ engineers and delivery centers worldwide, Mirafra has completed 650+ tape-outs for over 50 semiconductor customers, from startups to established firms. Its edge comes from a one-stop engineering partner model that combines deep domain expertise with scalable AI, cloud, data engineering, and software capabilities to speed time-to-market and reduce engineering complexity.
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