Engineer Front Assembly Line

Job Description

To develop, optimize, qualify, and establish robust semiconductor assembly processes for semiconductor packages, covering multiple assembly processes from wafer preparation to final assembly cleaning. The role is responsible for process development, optimization, qualification, technical problem-solving, and manufacturing readiness to ensure new products meet quality, reliability, productivity, and cost requirements.

The engineer will work closely with NPI project management, Production, Process Engineering, Equipment Engineering, Quality Assurance, Product Engineering, Material Engineering, and other cross-functional teams to ensure successful product introduction and smooth transfer to mass production.

Key Responsibilities

A. NPI Process Development and Qualification

• Develop, establish, and optimize assembly process conditions for new products.
• Prepare and execute process development plans, engineering & qualification builds, and process validation activities.
• Establish process parameters, specifications, control limits, and acceptance criteria.
• Evaluate process feasibility, identify potential manufacturing risks, and implement preventive actions before mass production.
• Review process capability, yield performance, defect trends, and qualification results.
• Prepare technical reports, process documentation, and qualification summaries.
• Support safe launch activities and ensure all critical process issues are resolved before mass production release.

B. Multi-Process Engineering Responsibilities

• Wafer Mounting – Develop and optimize wafer mounting processes for Normal and Taiko wafers
• Wafer Dicing - Develop and optimize dicing parameters, including blade selection and other related parameters
• Solder Printing – Frame/Die - Develop and optimize solder printing processes for LF’s or designated frame substrates and on die according to the design and process flow.
• Die Bonding - Develop and optimize die bonding processes applicable process parameters.
• Clip Bonding - Develop and optimize clip bonding process, clip alignment, and other applicable process parameters..
• Vacuum Reflow - Develop and optimize vacuum reflow profiles.
• Flux Cleaning - Develop and optimize Flux cleaning process

C. Cross-Functional Collaboration

• Collaborate with Production, Equipment Eng, QA, Product Eng, Material Eng, and other relevant departments
• Work with equipment and material suppliers to evaluate new technologies and improvement opportunities.
• Provide technical support during engineering builds, qualification builds, troubleshooting, and production ramp-up.
• Coordinate process readiness, material availability, and documentation before qualification and mass production.

D. Documentation and Mass Production Transfer

• Prepare and maintain process specifications, SOPs, work instructions, process flow documents, and risk assessments.
• Maintain engineering records, process parameter histories, DOE results, and qualification reports.
• Support PFMEA reviews and implementation of appropriate process controls.
• Define critical-to-quality parameters and monitoring requirements.

Qualifications

• Bachelor's Degree in Engineering (Electrical, Electronics, E&E, Mechanical, Mechatronics, Materials, Semiconductor, or related disciplines).
• Minimum 5 years experience in semiconductor assembly, packaging, or manufacturing engineering is preferred.
• Candidates with relevant experience in multiple assembly processes, particularly power semiconductor or power discrete packaging, will have an added advantage.

Skills and Knowledge

• Strong analytical, troubleshooting, and problem-solving skills.
• Good understanding of semiconductor assembly processes and process interactions.
• Knowledge of DOE, SPC, process capability analysis, FMEA, and structured root cause analysis.
• Ability to interpret engineering data, identify process risks, and implement effective corrective actions.
• Proficiency in Microsoft Excel and PowerPoint for data analysis, technical reporting, and presentation.
• Good communication and cross-functional collaboration skills.
• Ability to manage multiple NPI activities and meet project milestones.

Added Advantages

• Experience in MOSFET, power discrete, or power semiconductor package assembly.
• Hands-on experience in Taiko wafer handling, wafer dicing, solder printing, die bonding, clip bonding, vacuum reflow, and flux cleaning.
• Experience in solder joint inspection, void analysis, X-ray inspection, cross-section analysis, and package failure analysis.
• Experience in new product qualification, process transfer, safe launch, and mass production ramp-up.
• Experience in process development using DOE and optimization of multi-step assembly processes.

Additional Information

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us?

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.