Mythic

Power-efficient edge AI processors for inference

Senior Staff/Staff Engineer: Physical Design

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-timeBengaluru, Karnataka, IndiaNo salary listed

About the Job

Requirements

A B.Tech, M.Tech, or PhD in Electrical Engineering or Electronics & Communication Engineering is required.
At least 10 years of experience in the Physical Design domain is required.
Deep expertise in one or more of Synthesis, Formal Equivalence, Place and Route, Static Timing Analysis, or DRC/LVS/IR/EM signoff, with strong working knowledge of the entire Physical Design flow, is required.
A proven track record of successful tapeouts for multi-million-gate, multi-hierarchy designs at advanced nanometer technology nodes is required.
A solid understanding of low-power design and implementation strategies is required; hands-on experience is preferred.
A strong background in automating Physical Design methodologies using TCL, PERL, or Python is required.
Willingness to expand beyond core expertise and commitment to mastering the full RTL-to-GDSII flow are required.
Knowledge of chiplet-based design limitations and their impact on physical design is desirable.
Experience in Sub-10nm designs is desirable.
Familiarity and hands-on experience with Cadence toolsets is desirable.

Responsibilities

Participate in developing Physical Design methodologies across the RTL-to-GDSII flow using industry-standard tools, including Cadence, Synopsys, and Mentor.
Perform lead-level hands-on work in one or more areas: Synthesis, Formal Equivalence, Place and Route, Static Timing Analysis, or DRC/LVS/IR/EM signoff, at module and top level.
Own the physical design process at the module level and support top-level integration, collaborating with RTL designers, DFT teams, and fabrication partners.
Provide technical mentorship, guide team members, and manage Physical Design team interactions to support successful SoC implementation.
Drive PPA optimization, including low-power clock tree design for high-performance systems, and achieve timing closure across multiple corners and use cases.
Develop automation-first methodologies using TCL, PERL, or Python to improve team efficiency.

Desired Qualifications

Solid understanding and preferably hands-on experience in low-power design and implementation strategies.
Knowledge of chiplet-based design limitations and their impact on physical design.
Experience in Sub-10nm designs.
Familiarity and hands-on experience with Cadence toolsets.

About us:

Mythic has developed a unified hardware and software platform featuring its unique Mythic Analog Compute Engine (Mythic ACE™) to deliver revolutionary power, cost, and performance that shatters digital barriers preventing AI innovation at the edge. Mythic's unique technology makes it much easier and more affordable to deploy powerful AI solutions, from the data center to the edge device. The company has raised over USD 125M in a recent funding round and has offices in Palo Alto (CA, USA), Austin (TX, USA), and Bangalore (Karnataka, India).

About This Role:

Mythic is a fast-paced AI startup seeking passionate engineers who thrive in dynamic environments and embrace broad, flexible roles. We are looking for hands-on Physical Design Engineers eager to push boundaries in advanced technology nodes. This role is for Mythic’s Bangalore design center, but as part of our global workforce across geographies, you will drive innovation by working closely with the RTL and Technology teams and contribute to producing high-quality designs through first-pass silicon success.

With end-to-end ownership, you’ll tackle challenges in physical design with a focus on scalability, speed of execution, and efficiency in a fast-moving AI hardware landscape, with a strong emphasis on analog IP integration. This role is for experienced, seasoned engineers who are well-versed in PD flows, with a proven record of execution, and who are driven to push the envelope and find innovative solutions to complex implementation challenges at both the subsystem and chip levels.

Here is what you will do:

Participate in the development of Physical Design (PD) methodologies across the RTL-to-GDSII flow using industry-standard tools (Cadence, Synopsys, Mentor).
Perform lead level hands-on work in one or more areas including Synthesis, Formal Equivalence, Place & Route (PnR), Static Timing Analysis (STA), DRC/LVS/IR/EM Signoff at both module and top level.
Take full ownership of the physical design process at the module level and provide support in top-level integration, collaborating closely with RTL designers, DFT teams, and fabrication partners.
Provide technical mentorship, guiding team members and managing PD team interactions to ensure successful SoC implementation.
Drive PPA optimization, including low-power clock tree design for high-performance systems, and achieve timing closure across multiple corners and use cases.
Champion an automation-first approach, developing methodologies in TCL, PERL, or Python to significantly improve team efficiency.

Here is the background we hope you have:

B.Tech/M.Tech/PhD in Electrical Engineering (EE) or Electronics & Communication Engineering (ECE).
10+ years of experience in the Physical Design domain.
Deep expertise in one or more areas (Synthesis, Formal Equivalence, PnR, STA, DRC/LVS/IR/EM signoff) with strong working knowledge of the entire PD flow.
Proven track record of successful tapeouts for multi-million gate, multi-hierarchy designs at advanced nanometer technology nodes.
Solid understanding and preferably hands-on experience in low-power design and implementation strategies.
Strong background in automation of PD methodologies using TCL, PERL, or Python.
Willingness to expand beyond core expertise, with a team-oriented, can-do attitude and commitment to mastering the full RTL-to-GDSII flow.

The following would be nice to have, but is not required:

Knowledge of chiplet-based design limitations and their impact on physical design.
Experience in Sub-10nm designs
Familiarity and hands-on experience with Cadence toolsets.

At Mythic, we pride ourselves in creating a culture where all employees feel valued and appreciated for the diverse perspectives and backgrounds they bring to the team. We aim to hire smart people, give them the resources they need to do their job well, and then leave the rest up to them. We celebrate individual differences and encourage people to be comfortable bringing their authentic selves to work. At the end of the day, we are committed to building a diverse workforce where everyone belongs.

Mythic is an equal opportunity and affirmative action employer. It ensures equal employment opportunity without discrimination or harassment based on race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity or expression, age, disability, national origin, marital or domestic/civil partnership status, genetic information, citizenship status, veteran status, or any other characteristic protected by law.

We look forward to reviewing your application!

About the Company

Mythic

Power-efficient edge AI processors for inference

Mythic designs power-efficient AI hardware for edge deployments. Its main products are the M1076 Analog Matrix Processor, a single-chip accelerator that can run at up to 25 TOPS, and the MP10304 Quad AMP PCIe card, which adds more performance for AI inference on edge devices and servers. The hardware uses analog matrix processing to perform AI computations with low energy usage, enabling high-performance inference in real-world environments without relying on cloud servers. Mythic targets customers that need strong AI performance with tight power budgets, such as tech companies and other businesses with heavy data-processing needs. Compared with typical AI accelerators, Mythic emphasizes analog computation and edge efficiency, offering a compact single-chip solution plus an expansion PCIe card to scale performance. The company's goal is to make high-performance AI inference practical at the edge by delivering power-efficient processors and modules for edge devices and servers.

Company size: 51-200
Company stage: Late Stage VC
Total funding: $290.4M
Headquarters: Austin, TX
Founded: 2012

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