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Eridu AI

AI-native networking chips for large clusters

Lead Hardware Engineer

Hardware Systems IntegrationUpdated on Nov 11
Full-timeTaipei City, TaiwanNo salary listed

About the Job

Requirements

  • A bachelor's degree in Electrical Engineering, Computer Engineering, or a similar technical degree is required.
  • At least 10 years of system-level development experience in the server, computer, or networking industries is required.
  • At least 5 years as a lead or manager in a technology-driven product company is required.
  • Demonstrated experience working with ODM/CM design teams through the full development and production lifecycle is required.
  • A solid understanding of high-speed design and signal and power integrity considerations is required.

Responsibilities

  • Work cross-functionally to turn high-level concepts into detailed hardware specifications.
  • Develop technology de-risk plans through supplier evaluation boards and early prototypes.
  • Apply high-speed design practices, including signal and power integrity analysis, to ensure robust designs.
  • Work with partners through schematic entry, layout, and manufacturability reviews.
  • Lead or participate in build reviews, holding the ODM accountable to quality, cost, and schedule commitments.
  • Drive hardware bring-up and signal-integrity and power-integrity validation plans.
  • Drive hardware qualification test plans and testing, including EDVT, MDVT, EMI/EMC, and safety.
  • Drive root-cause analysis and corrective actions for issues found during bring-up, qualification, or manufacturing.

Desired Qualifications

  • A master's degree in Electrical Engineering or Computer Engineering is preferred.
  • Outstanding knowledge of the hardware design process and design practices, demonstrated through a track record of delivering shipped products.
  • Proficiency in high-speed technologies, including Ethernet and PCIe.
  • Experience designing systems with standards-based optical interfaces, such as QSFP and OSFP.
  • Proficiency in control interfaces such as MDIO, SPI, I2C, and JTAG.
  • A good understanding of FPGA design, power circuits, and clocking.
  • A good understanding of mechanical and thermal considerations.
  • Experience leading formally or informally within a cross-functional team.

About the Company

Eridu AI

AI-native networking chips for large clusters

Eridu AI designs AI-native networking chips and systems that replace multi-hop optical tiers in large GPU training clusters. Their products place more networking functions on-chip within a redesigned switch stack, which reduces power consumption, cost, and latency as GPU bandwidth scales. This approach differs from traditional Arista-like gear by integrating switching functionality directly into silicon, aiming for highly scalable, energy-efficient networking for hyperscale cloud providers, AI labs, and enterprises running million-GPU-class clusters. The company targets large-scale GPU deployments and seeks to make data-center networking more efficient, scalable, and cost-effective, backed by substantial funding from major investors to support growth and deployment.

Company size
51-200
Company stage
Series A
Total funding
$230M
Headquarters
Saratoga, CA
Founded
2024

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