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Eridu AI

AI-native networking chips for large clusters

ASIC Design Verification Lead

Hardware Validation & TestingConfirmed live in the last 24 hours
Full-timeSaratoga, CA, USANo salary listedIn-person

About the Job

Requirements

  • Strong hands-on experience in ASIC design verification.
  • A proven track record of taking at least one complex ASIC to tape-out with direct verification ownership.
  • Deep expertise in SystemVerilog and Universal Verification Methodology (UVM)-based verification methodologies.
  • Strong understanding of ASIC design and verification flows, including simulation, coverage, and debug.
  • Experience with block-level through full-chip verification and integration.
  • Ability to drive execution in ambiguous, fast-paced startup environments.
  • Excellent communication skills and ability to collaborate across disciplines.

Responsibilities

  • Define and own block-, subsystem-, and chip-level verification strategies.
  • Develop and maintain scalable verification environments using SystemVerilog and Universal Verification Methodology (UVM).
  • Drive execution from test-plan definition through coverage and bug closure.
  • Ensure verification readiness as a gating requirement for tape-out.
  • Write and review high-quality testbenches, sequences, checkers, and scoreboards.
  • Develop constrained-random, directed, and stress tests to validate complex corner cases.
  • Actively debug functional failures across RTL, testbench, and simulation environments.
  • Define functional, code, and assertion coverage goals.
  • Analyze coverage results and identify verification gaps.
  • Provide clear, actionable feedback to RTL designers to improve design and test quality.
  • Partner closely with RTL, architecture, physical design, and firmware teams.
  • Drive root-cause analysis of functional, performance, and integration issues.
  • Support gate-level, timing-aware, and power-aware simulations as required.
  • Partner with and support emulation and post-silicon validation of the ASIC design.
  • Lead full-chip verification planning, execution, and closure.
  • Support emulation and acceleration environments where appropriate.
  • Ensure clean handoff to silicon bring-up teams with high confidence in design correctness.
  • Establish and enforce verification checklists and quality gates.
  • Track verification progress and risk, proactively escalating issues.
  • Lead by technical authority and hands-on contribution rather than coordination alone.
  • Continuously improve verification methodology, infrastructure, and best practices.

Desired Qualifications

  • Networking ASIC verification experience, preferably in Ethernet-based systems.
  • Experience with gate-level, timing-aware, and low-power verification.
  • Familiarity with high-speed interfaces and chip-to-chip interconnects.
  • Experience with emulation, acceleration, or FPGA-based validation.
  • Post-silicon debug experience and RTL-to-silicon correlation.

About the Company

Eridu AI

AI-native networking chips for large clusters

Eridu AI designs AI-native networking chips and systems that replace multi-hop optical tiers in large GPU training clusters. Their products place more networking functions on-chip within a redesigned switch stack, which reduces power consumption, cost, and latency as GPU bandwidth scales. This approach differs from traditional Arista-like gear by integrating switching functionality directly into silicon, aiming for highly scalable, energy-efficient networking for hyperscale cloud providers, AI labs, and enterprises running million-GPU-class clusters. The company targets large-scale GPU deployments and seeks to make data-center networking more efficient, scalable, and cost-effective, backed by substantial funding from major investors to support growth and deployment.

Company size
51-200
Company stage
Series A
Total funding
$230M
Headquarters
Saratoga, CA
Founded
2024

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