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Upscale AI

High-performance AI networking hardware and software

Staff ASIC Modeling Software Engineer

Software EngineeringConfirmed live in the last 24 hours
Full-timeSanta Clara, CA, USA$182k - $216k /yr

About the Job

Requirements

  • At least 7 years of experience in C/C++ architecture model development, cycle-aware simulation, or ASIC verification.
  • Expert-level programming proficiency in modern C++17.
  • Deep understanding of network switch/router architecture, including forwarding tables, scheduling, quality of service, and access control lists.
  • Experience with packet processing pipelines and dataplane simulation.
  • Familiarity with hardware description languages such as Verilog/SystemVerilog and the ability to read RTL.
  • Experience with gRPC, Protocol Buffers, or similar interprocess communication mechanisms.
  • Experience with C++ unit testing frameworks such as Google Test.
  • Familiarity with Python for test automation, tooling, and scripting.
  • Strong debugging skills across software and hardware domains.

Responsibilities

  • Design and implement software model components that accurately simulate ASIC behavior, including forwarding engines, schedulers, memory subsystems, and control plane interfaces.
  • Translate architectural specifications and microarchitecture documents into high-fidelity C++ models, ranging from functionally accurate to performance-accurate depending on the subsystem.
  • Develop and maintain the register model, memory map, and configuration interfaces.
  • Implement packet processing pipelines for multiple forwarding modes.
  • Optimize model performance for large-scale simulations.
  • Collaborate with RTL engineers to ensure model-to-silicon correlation.
  • Work with the architecture team to validate algorithm and architectural choices through simulation.
  • Work with SDK and platform software teams to enable software development and validation on the model.
  • Support multiple ASIC versions with a maintainable, configurable model architecture.

Desired Qualifications

  • Experience with AI/ML networking, including scale-up fabrics, RDMA, and collective operations.
  • Experience using ns-3 and/or HTSim to model high-performance network architectures.
  • Familiarity with SAI (Switch Abstraction Interface) or SONiC.
  • Experience with FPGA prototyping or emulation platforms.
  • Background in memory subsystem modeling, including DDR, HBM, and caches.
  • Experience with configuration-driven simulation frameworks using YAML, JSON, or protobuf-based configuration.

About the Company

Upscale AI

High-performance AI networking hardware and software

Upscale AI builds a full-stack, high-performance AI networking platform to scale up GPU compute. It designs purpose-built silicon chips and a software orchestration layer that connects thousands of GPUs into a single, unified compute engine. The system is optimized for the heavy data movement and bursty traffic of large language model training and inference, enabling fast, scalable AI workloads. Unlike traditional, vendor-driven networking stacks, Upscale AI offers open-standard networking powered by silicon and software, and participates in consortia like UEC and SONiC to ensure interoperability across different hardware environments. Its customers include global hyperscalers, AI-first enterprises, and sovereign cloud providers who need large-scale, interoperable AI clusters without lock-in. The company’s goal is to democratize AI infrastructure by delivering high-performance, open-standard solutions that let organizations build and operate massive AI clusters more efficiently.

Company size
201-500
Company stage
Series A
Total funding
$490M
Headquarters
Santa Clara, CA
Founded
2024

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