T

Tenstorrent

Designs AI chips and licenses processor cores

Senior DFT Engineer - Architecture

Full-TimeUpdated on 10/14/2026
No salary listed
Expert
Bachelor's, Master's, PhD
Tokyo, Japan
In Person
Hardware EngineeringHardware Validation & Testing

About the job

Requirements
  • A bachelor's, master's, or PhD degree in electrical engineering, computer engineering, or computer science.
  • At least 10 years of relevant industry experience.
  • Experience with DFT standard tools such as Synopsys or Siemens, and scripting languages such as TCL or Python.
  • Experience with DFT planning and silicon debug by making SOC.
  • Ability to develop a DFT plan, monitor key indicators, communicate resource needs, and scope risks to deliver value on schedule.
  • Fluency in English, both verbal and written.
  • Eligibility to access U.S. export-controlled technology, based on citizenship, permanent residency, or ability to obtain prior license approval, as required by U.S. export laws.
Responsibilities
  • Build chip-level DFT strategies.
  • Insert DFT features, including scan chains, memory BIST, and JTAG.
  • Collaborate with RTL, physical design, and verification teams to ensure testability throughout the design flow.
  • Script and automate DFT flows using industry-standard EDA tools such as Cadence, Synopsys, or Siemens.
  • Run and analyze ATPG and fault coverage reports.
  • Support silicon bring-up and debug related to test features.
  • Integrate and verify test features in digital designs for manufacturing testing and silicon debug.
  • Work on chiplet integration into a system-in-package in collaboration with external stakeholders.
Desired Qualifications
  • Fluency in Japanese.
  • Japanese work visa.
  • Knowledge of advanced silicon technologies and methodologies for test coverage optimization.
  • Experience with formal verification and signoff of inserted DFT logic.

About the company

Tenstorrent designs AI processors and computing systems for developers, enterprises and chip designers that want control over their hardware. Its Galaxy servers connect multiple AI processors to run language models, video generation and other workloads across larger systems. The company sells accelerator cards, workstations and servers, and licenses RISC-V CPU designs and Tensix AI cores for customers to incorporate into their own chips. Its software compilers translate models from popular machine learning frameworks into programs for Tenstorrent hardware. Founded in 2016, it operates from offices in the United States, Canada, Europe and Asia.

Company Size

501-1,000

Company Stage

Late Stage VC

Total Funding

$2.3B

Headquarters

Santa Clara, California

Founded

2016

Get referred to Tenstorrent

See people who can refer or advise you

Simplify Jobs

Simplify's Take

What believers are saying

  • Chip licensing reaches established manufacturers: Samsung and LG license Tenstorrent CPU and AI cores.
  • Research deployment extends beyond chatbots: September 2026 JapanFold launched drug discovery models using Tenstorrent Galaxy servers.
  • Toronto debug engineers learn across layers: Tenstorrent advertises experience spanning silicon, boards, firmware, drivers and system software.

What critics are saying

  • Model compatibility needs checking: experimental TT-Forge lacks some operators and support for changing tensor dimensions.
  • Remote flexibility is limited for Toronto debug engineers: Tenstorrent specifies hybrid attendance and hands-on lab work.
  • Hardware rollout includes delivery waits: Blackhole cards list two weeks to ship plus two to five weeks of transit.

What makes Tenstorrent unique

  • Memory uses standard graphics components: Tenstorrent Blackhole cards carry up to 32GB of GDDR6.
  • Outsiders shape the stack: Tenstorrent rewards merged compiler, firmware and kernel contributions through its discretionary bounty program.
  • Architecture leadership has shipped mainstream chips: CEO Jim Keller led designs behind AMD Zen and Apple A4/A5 processors.

Help us improve and share your feedback! Did you find this helpful?

Benefits

Hybrid Work Options

Growth & Insights and Company News

Headcount

6 month growth

0%

1 year growth

2%

2 year growth

6%
CxOToday
Oct 8th, 2026
Vayavya Labs and Tenstorrent partner to accelerate RISC-V hardware and software development through virtual platform modeling.

Vayavya Labs and Tenstorrent partner to accelerate RISC-V hardware and software development through virtual platform modeling. Vayavya Labs and Tenstorrent are delivering SystemC virtual platforms for Tenstorrent's security and system management IP using the TvastaaVP platform. Vayavya Labs announced its role as a virtual platform partner to Tenstorrent, an AI compute company building RISC-V-based processors and systems. Since 2024, Vayavya Labs has built and delivered SystemC/TLM virtual platforms modeling subsystems of Tenstorrent's IP portfolio, including security enclave processor (SEP) register complexes, system management controller (SMC) logic, direct memory access (DMA) engines with secure zeroing, boot and fuse infrastructure, and a hardware security module supporting cryptographic operations. These models allow Tenstorrent's software and validation teams to develop, test, and debug against a virtual representation of the hardware well before physical silicon is ready, helping identify integration issues earlier in the development cycle. Vayavya Labs built the models on CSML, its SystemC modeling library, providing Tenstorrent with an open, Accellera-compatible modelling path and a commercial variant tuned for its simulation environment. Vayavya Labs used TvastaaVP to accelerate development while maintaining quality controls. Most recently, Vayavya Labs delivered a phased release of Tenstorrent's Open Chiplet Harness SEP virtual platform on two independent simulation targets and extended the platform with an additional system management controller and harness capabilities. "Getting software and validation teams working against accurate models before silicon is available provides a meaningful advantage in this industry and a faster time to market. "It's one of the primary reasons we've continued to deepen our work with Vayavya Labs," said Aniket Saha, VP of Product Strategy, Tenstorrent. "Tenstorrent is exactly the kind of production environment where agentic AI for virtual prototyping has to deliver production IP, demanding schedules, and high-quality bars," said Sandeep Pendharkar, CTO & VP Engineering, Vayavya Labs. "What started as a single SystemC modeling engagement has grown into a multi-year partnership precisely because the models hold up under that pressure. As Tenstorrent's RISC-V roadmap continues to expand, we see this as just the beginning of what virtual platforms can do for development velocity." Vayavya Labs and Tenstorrent will discuss this collaboration further at The Open Frontier, Tenstorrent's RISC-V ecosystem event in Bengaluru on October 8, 2026, where Sandeep Pendharkar, CTO & VP Engineering at Vayavya Labs, will join the panel "Latest in RISC-V Products & Startups," moderated by Tenstorrent's Divyang Agrawal, VP of RISC-V Cores/IP.

PR Newswire
Oct 7th, 2026
Vayavya Labs and Tenstorrent partner to accelerate RISC-V hardware and software development through virtual platform modeling.

Vayavya Labs and Tenstorrent partner to accelerate RISC-V hardware and software development through virtual platform modeling. Vayavya Labs Oct 07, 2026, 08:30 ET Vayavya Labs and Tenstorrent are partnering to build SystemC virtual platforms that enable earlier software development and validation for Tenstorrent's RISC-V hardware, reducing integration risks and time to market. BELAGAVI, India and SANTA CLARA, Calif., Oct. 7, 2026 /PRNewswire-PRWeb/ - Vayavya Labs and Tenstorrent are delivering SystemC virtual platforms for Tenstorrent's security and system management IP using the TvastaaVP platform. Vayavya Labs, a Silicon-to-Systems technology solutions company specializing in hardware-software interface tools, ECU virtualization, and SystemC-based virtual prototyping, announced its role as a virtual platform partner to Tenstorrent, an AI compute company building RISC-V-based processors and systems. Since 2024, Vayavya Labs has built and delivered SystemC/TLM virtual platforms modeling subsystems of Tenstorrent's IP portfolio, including security enclave processor (SEP) register complexes, system management controller (SMC) logic, direct memory access (DMA) engines with secure zeroing, boot and fuse infrastructure, and a hardware security module supporting cryptographic operations. These models allow Tenstorrent's software and validation teams to develop, test, and debug against a virtual representation of the hardware well before physical silicon is ready, helping identify integration issues earlier in the development cycle. Vayavya Labs built the models on CSML, its SystemC modeling library, providing Tenstorrent with an open, Accellera-compatible modelling path and a commercial variant tuned for its simulation environment. Vayavya Labs used TvastaaVP to accelerate development while maintaining quality controls. Most recently, Vayavya Labs delivered a phased release of Tenstorrent's Open Chiplet Harness SEP virtual platform on two independent simulation targets and extended the platform with additional system management controller and harness capabilities. "Getting software and validation teams working against accurate models before silicon is available provides a meaningful advantage in this industry, and a faster time to market. It's one of the primary reasons we've continued to deepen our work with Vayavya Labs," said **Aniket Saha, VP of Product Strategy, Tenstorrent**. "Tenstorrent is exactly the kind of production environment where agentic AI for virtual prototyping has to deliver - production IP, demanding schedules, and high quality bars," said Sandeep Pendharkar, CTO & VP Engineering, Vayavya Labs. "What started as a single SystemC modeling engagement has grown into a multi-year partnership precisely because the models hold up under that pressure. As Tenstorrent's RISC-V roadmap continues to expand, we see this as just the beginning of what virtual platforms can do for development velocity." Vayavya Labs and Tenstorrent will discuss this collaboration further at **The Open Frontier**, Tenstorrent's RISC-V ecosystem event in Bengaluru on October 8, 2026, where Sandeep Pendharkar, CTO & VP Engineering at Vayavya Labs, will join the panel "Latest in RISC-V Products & Startups," moderated by Tenstorrent's Divyang Agrawal, VP of RISC-V Cores/IP. About Tenstorrent Tenstorrent is an AI compute company led by CEO Jim Keller - architect of Apple A4/A5, AMD Zen, and Tesla's Full Self-Driving chip. The company builds RISC-V-based AI processors and systems for developers, enterprises, and sovereign infrastructure worldwide. In addition to servers and workstations, Tenstorrent licenses its TT-Ascalon RISC-V CPU and Tensix AI cores to chip designers. Backed by leading technology and financial investors, Tenstorrent has raised more than $1 billion and operates from Santa Clara, Austin, Toronto, Belgrade, Tokyo, and Bengaluru. About Vayavya Labs Vayavya Labs is a Silicon-to-Systems technology solutions company headquartered in Belagavi, India, with a development center in Bengaluru. Vayavya Labs specializes in hardware-software interface tools, Digital Twins, ECU virtualization, ADAS verification & validation services, and agentic AI platforms for SystemC-based virtual prototyping, serving semiconductor and automotive customers worldwide. Media Contact Justin Mauldin, Salient PR, 1 001-737.234.0936, [email protected], salientpr.com SOURCE Vayavya Labs

INSAIT
Sep 4th, 2026
Vanja Kovinić joins INSAIT as a Ph.D. Student.

Vanja Kovinić joins INSAIT as a Ph.D. Student. September 4, 2026 INSAIT is excited to welcome Vanja Kovinić to INSAIT as a new Ph.D. student! Vanja will pursue his Ph.D. in computer vision under the supervision of Dr. Danda Pani Paudel and Prof. Luc Van Gool. His research interests include 3D Computer Vision, Self-Supervised Learning, and World Models. Before joining INSAIT, Vanja worked as an AI Compiler Engineer at Tenstorrent, where he contributed to an open-source MLIR-based compiler and helped expand model support to 500+ AI models across vision, language, and other domains. He also gained research experience at the University of Illinois Urbana-Champaign, working on mixed-precision quantization. Vanja holds a B.Sc. and M.Sc. in Computer Science from RAF, Union University in Belgrade. Welcome to INSAIT, Vanja! INSAIT is looking forward to having you with INSAIT and following your research journey.

Healthcare Industry Today
Sep 3rd, 2026
ai& and Tenstorrent launch JapanFold, bringing open-source, sovereign drug discovery to Japan.

ai& and Tenstorrent launch JapanFold, bringing open-source, sovereign drug discovery to Japan. Japan should never have to choose between world-class AI and data sovereignty. JapanFold removes that trade-off entirely - frontier drug discovery, open-source, sovereign, and fully in-country." - David Bennett, CEO and co-founder, ai& YOKOHAMA, JAPAN, September 2, 2026 /EINPresswire.com/ - ai& and Tenstorrent launched JapanFold, a drug discovery platform running on ai&'s sovereign infrastructure, powered by Tenstorrent Galaxy(TM) superclusters. Japanese researchers, pharmaceutical companies, and biotech firms can now access frontier drug discovery models at a fraction of the cost of conventional cloud infrastructure, with every computation running entirely within Japan. JapanFold serves the leading open-source structural biology models: - Boltz-2, OpenFold3, ESMFold-2, OpenDDE, Protenix-v2, RoseTTAFold3, OpenBind-0, and Nesso-1 for structure and binding affinity prediction, - BoltzGen, RFdiffusion 3, and PXDesign for de novo drug design, covering the full discovery workflow from protein folding through drug candidate generation, and - ESMC and SaProt for protein embeddings to support downstream tasks ai& optimizes and serves every JapanFold model on Tenstorrent processors, delivering 1:1 accuracy without the cost premium - because the models scale nearly linearly on Tenstorrent hardware, doubling the number of processors doubles output. "Japan's research community should never have to choose between world-class AI and keeping their data sovereign. JapanFold removes that trade-off entirely - frontier drug discovery, open-source, sovereign, and fully in-country," said David Bennett, CEO and co-founder, ai&. JapanFold is accessible in three ways: - Workbench: Fold and design proteins directly in the browser. No install, no sign-up. - API: One HTTP endpoint for every model at api.japanfold.aiand.com/. - Agent Skill: Plain-language access from Claude Code, Cursor, Codex, and more. "Scalable hardware and open-source models are changing what's possible in biology and drug discovery," said Jim Keller, CEO of Tenstorrent. "Tenstorrent delivers fast, scalable compute, and ai& owns the full stack in Japan. Together, we've turned it into a platform researchers can actually use with JapanFold." The launch of JapanFold is the first step in ai& and Tenstorrent's broader effort to make sovereign, open-source AI infrastructure available to scientific research communities across the region. About ai& ai& is a global AI technology company founded on the simple conviction that whoever owns and optimizes the full stack wins. By integrating next-generation data center infrastructure, heterogeneous compute, and frontier model services into a single optimized platform, ai& gives enterprises and developers the performance, economics, and data sovereignty that no single-layer provider can match. Founded in Japan and expanding globally, ai& is building the foundation for the AI-native future. About Tenstorrent Tenstorrent is an AI compute company led by CEO Jim Keller - architect of Apple A4/A5, AMD Zen, and Tesla's Full Self-Driving chip. The company builds RISC-V-based AI processors and systems for developers, enterprises, and sovereign infrastructure worldwide. In addition to servers and workstations, Tenstorrent licenses its TT-Ascalon RISC-V CPU and Tensix AI cores to chip designers including Samsung and LG. Backed by Bezos Expeditions, Samsung, LG Electronics, Hyundai Motor Group, Fidelity, and others, Tenstorrent has raised over $1B+ and operates from Santa Clara, Austin, Toronto, Belgrade, Tokyo, and Bangalore. Legal Disclaimer: EIN Presswire provides this news content "as is" without warranty of any kind. Healthcare Industry Today do not accept any responsibility or liability for the accuracy, content, images, videos, licenses, completeness, legality, or reliability of the information contained in this article. If you have any complaints or copyright issues related to this article, kindly contact the author above.

Read Magazine
Aug 5th, 2026
SanDisk and SK hynix release first OCP specification for High Bandwidth Flash for AI Memory wall.

SanDisk and SK hynix release first OCP specification for High Bandwidth Flash for AI Memory wall. August 5, 2026 As the global artificial intelligence economy shifts rapidly from model training to large-scale inference deployment, the semiconductor industry faces an acute physical challenge known as the memory wall. Modern large language models (LLMs) demand immense bandwidth positioned close to compute cores to process tokens efficiently. However, while High Bandwidth Memory (HBM) offers extraordinary speed, its capacity limitations and high costs create severe economic barriers for hyperscale AI deployment. Conversely, conventional NVMe Solid State Drives (SSDs) deliver massive storage density but suffer from throughput bottlenecks that stall high-speed inference processing. To eliminate this memory tier gap, flash memory pioneer SanDisk Corporation and memory leader SK hynix Inc. announced the release of the first official High Bandwidth Flash (HBF(TM) technical specification through the Open Compute Project (OCP). Published six months after the OCP HBF workstream was established in February, the open specification establishes a technical framework for integrating high-density 3D NAND flash directly into near-compute memory hierarchies. Hyperscale AI giant Google and AI processor innovator Tenstorrent joined the alliance as core consortium members, validating the specification against real-world data center workloads. Discover more Social Sciences Engineering & Technology Agriculture & Forestry A Universal blueprint for High Bandwidth Flash. The OCP HBF specification provides chip designers and data center operators with an open framework to integrate HBF alongside HBM and conventional DRAM. By establishing electrical, physical, and protocol guidelines, the alliance enables AI accelerator designers to build flexible systems that increase near-compute memory capacity while lowering total cost of ownership (TCO). Machine Learning & Artificial Intelligence Key technical highlights of the open OCP HBF specification include: UCIe Interconnect Standardization: Utilizes the Universal Chiplet Interconnect Express (UCIe) interface, allowing HBF modules to connect seamlessly with GPUs, CPUs, and custom ASICs. Massive Near-Compute Density: Defines 8-layer and 16-layer 3D NAND stacking configurations delivering up to 512GB of capacity per stack - providing up to 16x the capacity of HBM stacks at lower costs. Multi-Grade Bandwidth Performance: Establishes three performance tiers delivering data throughput from 0.4 TB/s up to 3.0 TB/s, bringing flash storage into near-memory performance thresholds. Open Ecosystem Alignment: Published under the Open Compute Project framework to position HBF as the de facto standard across data centers, preventing vendor lock-in. "AI inference is creating a new set of memory requirements, and HBF technology is designed to meet that moment," stated Alper Ilkbahar, Chief Technology Officer at SanDisk. Engineering & Technology Impact on the semiconductor industry. The release of the HBF specification by SanDisk, SK hynix, Google, and Tenstorrent marks a major structural evolution across the Semiconductors sector: 1. Redefining the Global AI Memory Hierarchy Historically, the memory hierarchy was divided between volatile DRAM/HBM and non-volatile NAND flash drives. The standardization of HBF establishes Tiered Near-Compute Storage. Positioning 3D NAND within a high-speed UCIe interconnect envelope creates an intermediate layer that absorbs massive LLM parameter weights, reducing expensive HBM capacity demands while eliminating PCIe storage bus bottlenecks. 2. Accelerating UCIe Chiplet Ecosystem Adoption Integrating HBF technology via UCIe host interfaces provides a commercial catalyst for advanced packaging and chiplet integration. As memory makers stack 375-layer 4D NAND dies alongside logic dies, the supply chain will see increased capital expenditure toward advanced silicon interposers and 3D chiplet packaging. Overall effects on businesses operating in the sector. For hyperscale cloud providers, AI silicon startups, and enterprise OEMs, the standardized HBF platform delivers direct strategic benefits: Lowering Capital Expenditure for AI Deployments: Integrating lower-cost 3D NAND into near-compute tiers allows cloud providers like Google to serve multi-billion parameter LLMs at lower capital costs per query. Leveling the Playing Field for Startups: Open UCIe-compliant HBF specifications enable non-traditional chipmakers (such as Tenstorrent) to design high-performance AI inference accelerators without building custom memory controllers. Creating New Revenue Streams for Foundries: The emergence of HBF provides NAND flash manufacturers with a high-margin product category, reducing exposure to consumer SSD price cycles. Conclusion. The release of the first OCP High Bandwidth Flash specification by SanDisk and SK hynix represents a defining moment for semiconductor architecture. By combining high-density 3D NAND flash with near-memory bandwidth and open UCIe chiplet connectivity, these industry leaders are dismantling the AI memory wall. For the semiconductor industry, this milestone confirms that the future of scalable AI computing belongs to open, tiered memory architectures capable of delivering massive intelligence at scale.