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Astera Labs

Designs chips that connect data center systems

ATE Engineer Intern - Engineering Ops Technology Intern

Hardware Validation & TestingConfirmed live in the last 24 hours
InternshipSan Jose, CA, USAIn-person

About the Job

Requirements

  • Enrollment in a bachelor’s, master’s, or Ph.D. program in electrical engineering, computer engineering, computer science, or a related field.
  • Coursework, research, or project experience in digital systems, electronics, semiconductor testing, embedded systems, computer architecture, or hardware/software integration.
  • Programming or scripting experience in Python, C, C++, or a comparable language.
  • Familiarity with Linux or other development environments, Git, command-line tools, data analysis, and technical documentation.
  • Ability to follow structured test procedures, troubleshoot with data, and explain results clearly.
  • Enrollment in a bachelor’s, master’s, or Ph.D. program in computer science, information systems, industrial engineering, data science, electrical engineering, business analytics, or a related field.
  • Coursework, research, or project experience in software development, data analysis, process improvement, automation, operations research, or technology implementation.
  • Experience with Python, SQL, spreadsheets, scripting, APIs, or another tool used to analyze data and automate workflows.
  • Ability to learn unfamiliar systems, organize ambiguous problems, and translate stakeholder needs into practical technical solutions.
  • Strong written and verbal communication skills, including the ability to explain technical work to non-specialist audiences.

Responsibilities

  • Review product specifications, DFT requirements, and test objectives to help define ATE test coverage.
  • Support the creation and maintenance of ATE test plans, coverage matrices, checklists, characterization plans, and technical documentation.
  • Develop, debug, and improve test scripts or test-program components for functional, parametric, loopback, and interface testing.
  • Work with ATE firmware and tester control flows, including configuration handshakes, register or CSR access, status polling, power-cycle sequencing, and diagnostic data collection.
  • Support PCIe and high-speed interface validation using loopback, PRBS, link-status, error-count, and BER-oriented test flows where applicable.
  • Help bring up and validate load boards, probe cards, and related test hardware; investigate connectivity, power, reset, flash, and board-level issues.
  • Run characterization across operating conditions such as voltage, temperature, process, speed, and other defined corners; organize data and summarize findings.
  • Analyze yield, coverage, failure patterns, test stability, and test time to identify opportunities for better screening and lower manual effort.
  • Reproduce failures, compare expected and observed behavior, and collaborate with firmware, product, hardware, and quality engineers on corrective actions.
  • Support controlled release of test programs and documentation, including revision control, review evidence, handoff materials, and manufacturing readiness.
  • Present the completed project, conclusions, reusable artifacts, and remaining questions to the broader engineering team.
  • Interview engineering and operations stakeholders to understand workflow pain points, dependencies, current tools, and desired outcomes.
  • Map current-state processes and identify opportunities to reduce manual effort, improve handoffs, increase data visibility, or standardize execution.
  • Build prototypes, scripts, dashboards, or lightweight applications that automate recurring work and make engineering information easier to use.
  • Help unify, clean, and analyze data from engineering systems, project trackers, reports, logs, or spreadsheets.
  • Create repeatable workflows for reporting, issue triage, project tracking, documentation, onboarding, or operational reviews.
  • Support the evaluation and piloting of technology solutions, including requirements gathering, vendor or tool comparisons, security considerations, user testing, and rollout planning.
  • Develop clear metrics for adoption, time saved, reduced errors, throughput, data quality, or other measurable business impact.
  • Partner with Engineering, Program Management, IT, Quality, Operations, and other functional teams to validate solutions and incorporate feedback.
  • Document system designs, process changes, user instructions, assumptions, and maintenance needs so solutions can be adopted by the team.
  • Communicate progress, decisions, blockers, and next steps through concise updates, demonstrations, and stakeholder reviews.
  • Deliver a reusable project outcome and present the solution, implementation approach, results, and recommendations at the end of the internship.

Desired Qualifications

  • Exposure to automated test equipment, semiconductor test, wafer sort, final test, DFT, production screening, or OSAT workflows.
  • Familiarity with PCIe, SerDes, high-speed links, PRBS, BER measurement, loopback testing, or interface diagnostics.
  • Experience with lab instruments, load boards, probe cards, fixtures, power supplies, oscilloscopes, logic analyzers, or serial/I2C/SPI/UART interfaces.
  • Experience developing test automation, analyzing large data sets, or building reports and dashboards for test results.
  • Familiarity with embedded firmware, cross-compilation, register-level debug, flashing, or hardware bring-up.
  • Experience improving test coverage, yield, reliability, throughput, or test time through structured experimentation.
  • Experience building dashboards, data visualizations, reports, workflow automations, or internal tools.
  • Familiarity with project tracking, issue management, documentation, collaboration, or business-process systems.
  • Exposure to data cleaning, database concepts, ETL, log parsing, observability, or data quality checks.
  • Experience with Power BI, Excel automation, low-code tools, cloud services, or AI-assisted productivity tools.
  • Familiarity with user research, requirements gathering, pilot design, change management, or measuring adoption and return on investment.
  • Experience working with engineering, hardware, manufacturing, quality, or other technical operations teams.

About the Company

Astera Labs

Designs chips that connect data center systems

Astera Labs designs chips and hardware modules that move data between processors, memory and accelerators in data centers. Its customers include cloud providers, chip vendors and equipment makers building servers and large computing clusters for AI and other workloads. Retimers restore signal quality, switches connect devices and memory controllers expand the memory available to computing systems, while COSMOS software monitors and manages these links. The company sells its products directly and through distributors, using outside manufacturers to fabricate and assemble its hardware. Astera Labs was founded in 2017 and is headquartered in San Jose, California.

Company size
501-1,000
Company stage
IPO
Headquarters
San Jose, CA
Founded
2017

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