DFT Engineer Manager

Role Overview

As a DFT Architect/Manager/Sr. Manager at Velaura AI, you will lead the definition, implementation, and execution of Design-for-Test strategies for next-generation AI and high-performance computing silicon. You will be responsible for driving test architecture, methodology, and implementation across complex ASIC/SoC designs, ensuring high test quality, manufacturability, reliability, and production readiness. You will work closely with architecture, RTL, verification, physical design, STA, validation, product engineering, and manufacturing teams to integrate robust DFT features into the silicon platform. This is a highly visible technical and leadership role where you will influence DFT architecture, lead complex execution across teams, drive methodology improvements, mentor engineers, and support successful silicon bring-up, yield ramp, and production quality.

Responsibilities

● Define and drive DFT architecture, strategy, and methodology for complex ASIC/SoC designs targeting AI and high-performance compute applications.

● Lead the planning and implementation of DFT features including scan insertion, compression, ATPG, MBIST, LBIST, boundary scan, JTAG, IJTAG, test access
mechanisms, and fault simulation.

● Own end-to-end DFT execution from architecture definition through RTL integration, implementation support, verification, pattern generation, sign-off, silicon bring-up, and production ramp.

● Collaborate with architecture, RTL, verification, physical design, STA, validation, test, product engineering, and manufacturing teams to ensure DFT requirements are integrated early and executed successfully.

● Develop comprehensive test plans to optimize fault coverage, reduce test cost, improve test quality, and ensure manufacturability.

● Drive ATPG pattern generation, coverage analysis, fault grading, diagnosis, and pattern validation across block, subsystem, and chip levels.

● Define and implement memory test strategies including MBIST architecture, repair analysis, redundancy handling, and memory test integration.

● Drive logic BIST, scan compression, at-speed testing, transition fault testing, stuck-at testing, path delay testing, and advanced fault model coverage.

● Lead DFT verification activities including simulation, formal verification, connectivity checks, test-mode validation, and pattern verification.

● Partner with physical design and STA teams to resolve DFT-related timing,congestion, test-mode constraints, scan reordering, and implementation closure challenges.

● Support post-silicon debug, yield analysis, failure diagnosis, production test correlation, and on-field failure analysis.

● Establish DFT quality metrics, sign-off criteria, coverage targets, and execution checkpoints across the design lifecycle.

● Evaluate, deploy, and improve DFT tools, flows, automation, and methodologies to enhance productivity, quality, and test efficiency.

● Lead and mentor DFT engineers, provide technical guidance, review execution quality, and help build a strong DFT engineering organization.

● Stay current with industry trends in DFT, silicon test, advanced-node test methodologies, automotive-grade quality, and production test strategies.

Required Qualifications

● 15+ years of experience in DFT architecture, implementation, and sign-off for ASIC/SoC designs.

● Strong background in compute, AI, high-performance SoC, networking, processor, GPU, accelerator, or complex digital silicon designs.

● Proven experience defining and leading DFT strategy for large-scale ASIC/SoC programs from concept through silicon production.

● Strong expertise in scan design, scan compression, ATPG, MBIST, LBIST, JTAG, boundary scan, IJTAG, test access architecture, and fault simulation.

● Hands-on experience with ATPG pattern generation, coverage closure, pattern validation, diagnosis, and silicon correlation.

● Experience leading DFT teams and managing complex cross-functional execution across multiple projects or design programs.

● Strong experience with post-silicon debug, yield improvement, failure diagnosis, production test support, and on-field failure analysis.

● Good understanding of DFT impact on RTL design, physical design, timing closure, low-power implementation, and sign-off.

● Experience working with industry-standard DFT and EDA tools for scan insertion, compression, ATPG, MBIST, LBIST, verification, and diagnosis.

● Familiarity with advanced fault models, at-speed testing, transition delay testing, stuck-at testing, path delay testing, cell-aware test, and timing-aware ATPG.

● Strong analytical, debugging, problem-solving, communication, and technical leadership skills.

● Ability to work effectively in a fast-paced environment with geographically distributed teams.

Preferred Qualifications

● Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Electronics Engineering, VLSI, or a related discipline.

● Experience with advanced-node ASIC/SoC designs and high-volume production silicon.

● Experience with AI accelerators, high-performance compute, CPU, GPU, NoC, memory subsystem, or complex SoC architectures.

● Familiarity with automotive or functional safety standards such as ISO 26262 is preferred.

● Experience developing DFT methodologies for low-power designs, including UPF-aware test strategies, power domain testing, isolation, retention, and test-mode power management.

● Good understanding of Static Timing Analysis, test-mode constraints, scan timing, OCC, clocking, reset architecture, and multi-mode test closure.

● Experience with silicon bring-up, ATE pattern deployment, production test debug, yield ramp, and manufacturing quality improvement.

● Experience building automation using Tcl, Python, Perl, or other scripting languages.

● Track record of leading technical initiatives, mentoring engineering teams, and driving methodology improvements.

● Experience with sub-5nm or leading-edge technology nodes.

● Experience with automotive-grade silicon quality, reliability requirements, or ISO 26262-compliant development flows.

● Knowledge of advanced test methodologies including cell-aware test, timing-aware ATPG, hierarchical DFT, streaming scan networks, and adaptive test.

● Experience with memory repair, redundancy analysis, fuse flows, and production repair strategies.

● Familiarity with ATE platforms, test program development, pattern conversion, and tester correlation.

● Exposure to silicon lifecycle management, in-system test, on-chip monitors, and field diagnostics.

● Experience with security-aware test, debug access control, or secure JTAG methodologies.

● Strong technical leadership, mentoring, communication, and cross-functional collaboration skills.

● Passion for building robust, high-quality silicon and driving test innovation under aggressive product schedules.

● Background in DFT architecture and methodology for complex ASIC/SoC designs; scan insertion, scan compression, ATPG, MBIST, LBIST, JTAG, boundary scan, and IJTAG; AI compute, processor, GPU, accelerator, networking, or high-performance SoC test; fault simulation, coverage closure, pattern generation, and diagnosis; post-silicon debug, yield improvement, silicon correlation, and production test support; low-power and advanced-node DFT implementation; DFT verification, test-mode validation, and sign-off; cross-functional silicon development with RTL, verification, physical design, STA, validation, and manufacturing teams; or DFT tool flow development, automation, and methodology improvement.