Envision Employment Solutions

Lead STA Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-timeNew Cairo City, Cairo Governorate, EgyptNo salary listedIn-person

About the Job

Requirements

At least 10 years of physical design experience, with a strong focus on static timing analysis and timing signoff.
Proven experience leading timing closure on complex systems-on-chip at 10 nm or below.
Expert-level knowledge of PrimeTime and/or Tempus, including PTSI.
Deep understanding of Synopsys Design Constraints, multimode multicorner analysis, and variation modelling.
Strong scripting skills in Tcl, Perl, and Python.
Experience leading or mentoring engineers.
Multiple successful tapeouts as timing owner.

Responsibilities

Lead full-chip and block-level static timing analysis and timing signoff on advanced nodes of 10 nm and below.
Define timing methodology, signoff criteria, corners, and modes.
Own signal-integrity and noise analysis, on-chip variation strategies (OCV/AOCV/POCV), and signoff closure.
Drive engineering change order generation and implementation for timing and functional fixes.
Review and guide constraint quality across RTL, synthesis, and place-and-route teams.
Mentor and lead a team of timing engineers.
Build and improve timing automation and reporting flows.

Lead STA Engineer

Envision Employment Solutions · New Cairo City, Egypt · Full-time · Posted 2026-09-26

Workplace: on_site

Department: Semiconductor Engineering

Description

Envision Employment Solutions is currently looking for a Lead STA Engineer for one of our partners, an IT Services and IT Consulting company.

THE ROLE

Timing signoff is the final word on whether a chip is ready, and you'll be the one giving it. As the lead STA specialist, you'll set the timing methodology, guide the team through closure, and make the call on what's truly clean. You'll be the reference point for anyone who needs to understand why a path is failing and what it will take to fix it.

WHAT YOU'LL DO

Lead full chip and block level STA and timing signoff on advanced nodes (10nm and below)
Define timing methodology, signoff criteria, corners and modes
Own SI and noise analysis, OCV/AOCV/POCV strategy, and signoff closure
Drive ECO generation and implementation for timing and functional fixes
Review and guide constraint quality across RTL, synthesis and PnR teams
Mentor and lead a team of timing engineers
Build and improve timing automation and reporting flows

WHAT WE'RE LOOKING FOR

10+ years of physical design experience, with a strong focus on STA and timing signoff
Proven experience leading timing closure on complex SoCs at 10nm or below
Expert level knowledge of PrimeTime and/or Tempus, including PTSI
Deep understanding of SDC, multimode multicorner analysis and variation modelling
Strong scripting in Tcl, Perl and Python
Experience leading or mentoring engineers
Multiple successful tapeouts as timing owner

YOU'LL THRIVE HERE IF YOU

You're the one people call when nobody can explain a timing report
You set the standard rather than follow someone else's
You enjoy growing engineers as much as closing paths
You can hold a firm line on signoff quality under schedule pressure
You think in corners, modes and margins without having to try

Apply

Apply at Envision Employment Solutions

About the Company

Envision Employment Solutions

Company size: Not listed
Company stage: Not listed
Total funding: Not listed
Headquarters: Not listed
Founded: Not listed

Recently Posted Jobs

Explore more opportunities at Envision Employment Solutions

See more jobs